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Difference between revisions of "Optimal System Duty Cycling for a Mobile Health Platform"

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*30% Software adaption/extension
*30% Software adaption/extension
*50% Experiments/Measurements
*50% Experiments/Measurements
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[[Category:Biomedical System on Chips]]
[[Category:Biomedical System on Chips]]

Latest revision as of 16:57, 12 July 2022

Basic tradeoff mechanism between clock- (left) and power gating (right).

To meet the power requirements of wearable and implantable devices, duty cycling of unused components is a crucial mechanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level duty cycling of the PULP processing subsystem on our main ASIC VivoSoC.

As in every clocked digital circuit, the power consumption consists of leakage power that depends on the supply voltage and dynamic power which depends linearly on the operation frequency and quadratically on the supply voltage. By disabling the clock signal on idle parts of a circuit (called clock gating), the dynamic power can be eliminated and operation of the circuit quickly restored when needed. Also, the circuit overhead to enable clock gating is very small and hence fine-grain duty cycling is achievable. However, the leakage power continues to be consumed during idle periods, leading to wasted energy (see figure on the right).

To overcome this limitation, the concept of power gating allows to switch off the supply voltage of unused circuit partitions, eliminating any power consumption. Besides significantly higher design overhead, the major drawback of power- compared to clock gating is the loss of the state of the circuit (value of all sequential/storing elements). To continue operation after an idle period, the prior state must first be restored. In processing systems like PULP this translates mostly to a reboot of the processing cores, making them ready for further computations. Naturally, this process consumes parasitic energy, labeled Ereboot in the figure.

The goal is to combine both techniques in a way that leads to the minimum amount of energy used for a given task as the required energy dictates battery size, the most critical factor in any volume-constrained system.

We already successfully applied coarse- and fine grain clock gating in our applications, however so far only the concept of power gating has been proven to work. In this project, you are going to adapt an existing application to use the power gating capabilities of VivoSoC to further reduce the power consumption. Besides VivoSoC, we have a custom power management IC prototype with programmable voltage converters and uController available. Your job is to combine both ASICs, establish power-management related communication and handshaking between them and find a set of supply voltages, task scheduling and idle periods that minimizes energy consumption.

  • Example application with clock gating.
  • Communication between VivoSoC and the power management IC.

The figures above show all required ingredients are working: An application with clock gating enabled (left) and supply management between the ASICs (right). Now is the time to bring everything together and explore the resulting design space. Contact us for this exciting project!

Status: Available

We are looking for 1-2 motivated Semester Thesis students
Contact: Florian Glaser


  • Experience with embedded/low level software
  • Basic knowledge of the C language
  • Interest in embedded systems and uControllers


  • 20% Theory/Concept
  • 30% Software adaption/extension
  • 50% Experiments/Measurements