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PREM Intervals and Loop Tiling

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Increased computational requirements of embedded software, in real-time domains such as automotive and avionics, demand an increasing amount of performance, that can not be offered from traditional single-core systems used within these fields. While more powerful platforms, have long been available on the consumer market, their adoption into safety critical fields has been slow, due to the rigorous safety certification requirements. Such platforms include multi-core CPU processors and heterogeneous CPU + accelerator system-on-chips (SoCs). Enabling the use of heterogeneous platforms in safety-critical systems does not only offer a major increase in performance, but also promises an increase in energy efficiency due to the use of more efficient accelerators. However, characteristic for these platforms that the operation of one core may interfere with an other due to the sharing of hardware resources. Therefore, one of the most important factors for certification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the set deadlines.

A promising method to achieve this is the Predictable Execution Model (PREM). The fundaments of the PRedictable Execution Model (PREM) is the separation of memory and compute operations within programs, such that memory operations can be independently scheduled to provide freedom from interference -- i.e., only a single core is able to use the memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory phase is tasked with copying all data needed for computation into core-local private memories, such that the compute operations can be executed independently.


The goal of this project is to extend the PREM Compiler developed at IIS with an improved tiler, to enable better selection of PREM intervals from loops. Tiling is the process of dividing one loop into multiple smaller loops, typically used to improve cache locality. The student is expected to survey the techniques available in the scientific literature, and select a promising candidate for implementation. Important considerations are the efficiency of the tiler, both during compile time and execution time, as well as compatibility with the current compiler infrastructure.

Status: Available

Looking for 1 Interested Master Student (Master/Semester Project)
Supervision: Bjoern Forsberg


Knowledge on Memory Hierarchies
Interest in compiler techniques
Interest in real-time systems (this project does not cover real-time schedulability analysis)

The course Systems-on-chip for Data Analytics and Machine Learning provides a good fundament for the first two points on the list. Experience from Compiler Design and Embedded Systems is meriting.


Luca Benini

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