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PULP’s CLIC extensions for fast interrupt handling

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Overview

Status: In Progress

Introduction

Today’s real-time systems require fast interrupt handling to manage asynchronous requests coming from the surrounding environment, for example external master devices interacting with the system through I/O peripheral interfaces. This means that the underlying HW has to guarantee fast propagation of the interrupt lines towards the processor, with a per-interrupt, fine-grained control over each line, and support interrupt preemption and nesting according to each event priority.

Project

ControlPULP is a RISC-V, real-time platform envisioned as an integrated Power Management Unit. Developed at IIS, it is based on PULP [3] [4] [5] and relies on FreeRTOS [6] [7] to implement a Power Control Firmware (PCF) [8] routine. RISC-V Core Local Interrupt Controller (CLIC) [10] is an interrupt controller for RISC-V cores subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts.

An implementation of the CLIC has been developed at IIS [9] and integrated in ControlPULP. It integrates most of the features described in the specifications. Nonetheless, the basic architecture can be extended - leveraging either HW and SW - to support additional features, such as dynamic switching between legacy CLINT and new CLIC interrupt controllers and the mnxti CSR for horizontal interrupts handling in machine mode [13]. Inspiration can be taken from existing CLIC implementations (Nuclei’s ECLIC [12], T-Head’s CLIC [11]).

The goal of this project is to extend the CLIC with the aforementioned additional features, and compare against the current baseline. In particular:

  • Study CLIC current specification draft [10] and PULP’s CLIC implementation [2]
  • Implement CLINT/CLIC dynamic switching to handle CLIC selection at runtime
  • Implement xnxti horizontal interrupt transition with non-vectored interrupts
  • Implement interrupt tail-chaining [12]
  • Synthesize the design, giving particular attention to the CLIC overhead with respect to the original baseline
  • ASIC Backend flow. The CLIC IP and extensions integrated in ControlPULP will be taped-out in TSMC65 nm technology.

Character

  • 15% Literature / architecture review
  • 20% RTL implementation
  • 20% Software layer
  • 25% Evaluation
  • 20% Backend

Prerequisites

  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Must have visited VLSI II in a previous semester or take it alongside the thesis
  • Knowledge of C programming language as from previous bachelor/master courses

References

[1] https://developer.arm.com/documentation/den0056/latest

[2] https://github.com/ARM-software/SCP-firmware/tree/master/module

[3] https://ieeexplore.ieee.org/document/8065010

[4] https://ieeexplore.ieee.org/document/8715500

[5] https://github.com/pulp-platform/pulp

[6] https://www.freertos.org/

[7] https://github.com/pulp-platform/pulp-freertos

[8] https://iis-git.ee.ethz.ch/giovanni.bambini/epi_pmu_ethz

[9] https://github.com/pulp-platform/clic

[10] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

[11] https://github.com/bluewww/opene906

[12] https://doc.nucleisys.com/nuclei_spec/isa/eclic.html

[13] https://riscv.org/technical/specifications/