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Difference between revisions of "PULP’s CLIC extensions for fast interrupt handling"

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<!-- IIntegration of Alibaba’s T-Head Opene906 processor in PULP -->
<!-- Integration of Alibaba’s T-Head Opene906 processor in PULP -->

Revision as of 20:06, 20 January 2022


Status: Available


Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1].


PULPissimo is an open-source, single core RISC-V microcontroller [5] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [4].

The goal of this project is to replace our in-house processor with T-Head’s Opene906:

  • Study T-Head’s opene906 source code.
  • For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
  • Integrate T-Head’s opene906 into PULPissimo to replace the existing processor developed by PULP, CV32E40P
  • Verify basic functional correctness in simulation
  • Synthesize the new processor, evaluate area and timing figures
  • ASIC Backend flow towards PULPissimo SoC tapeout


  • 15% Literature / architecture review
  • 30% RTL implementation
  • 30% Backend
  • 25% Evaluation


  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Must have visited VLSI II in a previous semester or take it alongside the thesis


[1] (GitHub repository)

[3] (GitHub repository)

[4] (GitHub repository)

[5] (GitHub repository)