Personal tools

PULP’s CLIC extensions for fast interrupt handling

From iis-projects

Revision as of 15:06, 5 August 2022 by Balasr (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search


Status: Completed


Today’s real-time systems require fast interrupt handling to manage asynchronous requests coming from the surrounding environment, for example external master devices interacting with the system through I/O peripheral interfaces. This means that the underlying HW has to guarantee fast propagation of the interrupt lines towards the processor, with a per-interrupt, fine-grained control over each line, and support interrupt preemption and nesting according to each event priority.


ControlPULP is a RISC-V, real-time platform envisioned as an integrated Power Management Unit. Developed at IIS, it is based on PULP [3] [4] [5] and relies on FreeRTOS [6] [7] to implement a Power Control Firmware (PCF) [8] routine. RISC-V Core Local Interrupt Controller (CLIC) [10] is an interrupt controller for RISC-V cores subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts.

An implementation of the CLIC has been developed at IIS [9] and integrated in ControlPULP. It integrates most of the features described in the specifications. Nonetheless, the basic architecture can be extended - leveraging either HW and SW - to support additional features, such as dynamic switching between legacy CLINT and new CLIC interrupt controllers and the mnxti CSR for horizontal interrupts handling in machine mode [13]. Inspiration can be taken from existing CLIC implementations (Nuclei’s ECLIC [12], T-Head’s CLIC [11]).

The goal of this project is to extend the CLIC with the aforementioned additional features, and compare against the current baseline. In particular:

  • Study CLIC current specification draft [10] and PULP’s CLIC implementation [2]
  • Implement CLINT/CLIC dynamic switching to handle CLIC selection at runtime
  • Implement xnxti horizontal interrupt transition with non-vectored interrupts
  • Implement interrupt tail-chaining [12]
  • Synthesize the design, giving particular attention to the CLIC overhead with respect to the original baseline
  • ASIC Backend flow. The CLIC IP and extensions integrated in ControlPULP will be taped-out in TSMC65 nm technology.


  • 15% Literature / architecture review
  • 20% RTL implementation
  • 20% Software layer
  • 25% Evaluation
  • 20% Backend


  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Must have visited VLSI II in a previous semester or take it alongside the thesis
  • Knowledge of C programming language as from previous bachelor/master courses