Difference between revisions of "PULP"
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This is a joint project between the [http://www.iis.ee.ethz.ch Integrated Systems laboratory (IIS)] of ETH Zurich (IIS) and the [http://www.dei.unibo.it/en/research/research-facilities/Labs/eess-energy-efficient-embedded-systems Energy-efficient Embedded Systems] (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW. | This is a joint project between the [http://www.iis.ee.ethz.ch Integrated Systems laboratory (IIS)] of ETH Zurich (IIS) and the [http://www.dei.unibo.it/en/research/research-facilities/Labs/eess-energy-efficient-embedded-systems Energy-efficient Embedded Systems] (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW. | ||
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+ | The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging. | ||
[mailto:lbenini@iis.ee.ethz.ch Inquiries] from interested partners are welcome. | [mailto:lbenini@iis.ee.ethz.ch Inquiries] from interested partners are welcome. |
Revision as of 18:45, 7 July 2015
PULP - an Open Parallel Ultra-Low-Power Processing-Platform
This is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.
Inquiries from interested partners are welcome.
....more to follow.... stay tuned!
Related Available Projects
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- Sound-Based Vehicle Classification and Counting (1-2S)
- Multi-Modal Environmental Sensing With GAP9 (1-2S)
- Event-based navigation on autonomous nano-drones
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Improved Collision Avoidance for Nano-drones
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Physics is looking for PULP
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- PVT Dynamic Adaptation in PULPv3
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Hardware Support for IDE in Multicore Environment
- Variability Tolerant Ultra Low Power Cluster
Related Chips
28nm
- Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
- Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
- Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
65nm
- Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 Kbyte memory (65nm)
- Artemis 4 core PULP system including FPU (65nm).
- Hecate 4 core PULP system with 2 shared FPUs (65nm).
- Selene 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
- Diana 4 core PULP system with FPUs designed using approximate computing techniques (65nm).
130nm
- Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter (130nm)
180nm
- Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
- Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
- Sid Large PULP chip with in-exact accelerators, LL version
- Diego Large PULP chip with in-exact accelerators, LVT version
- Manny Large PULP chip with in-exact accelerators, sub-threshold version