PULP - An Open Parallel Ultra-Low-Power Processing-Platform
This is a joint project between the Integrated Systems Laboratory (IIS) of ETH Zurich and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.
See our Main Project webpage, our GitHub project page or follow us on Twitter for up to date information.
Related Available Student Projects
- Event-based navigation on autonomous nano-drones
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Improved Collision Avoidance for Nano-drones
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Physics is looking for PULP
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- PVT Dynamic Adaptation in PULPv3
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Hardware Support for IDE in Multicore Environment
- Variability Tolerant Ultra Low Power Cluster
- Occamy A chiplet based design with 216 Snitch cores and an Ariane/CVA6 based manager core.
- Marsellus IoT processor based on PULPopen
- Kraken IoT Processor with 3 accelerators based on PULPopen. Total of 9x 32bit RI5CY cores.
- Thestral Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed to test fine grained power gating solutions.
- Vega Prototype version of GAP9 a further development from GAP based on PULPopen. Total of 10x 32bit cores, 1 fabric controller + 9 in the cluster.
- Baikonur Two Ariane cores (similar to Kosmodrom) and introducing Bowtruckle a many core system around the Snitch core.
- Poseidon A chip containing both PULPissimo (updated single core microcontroller with 32-bit core) and Ariane (64 bit RISC-V core)
- Kosmodrom The chip contains two instances of an improved Ariane cores (with FPUs) optimized for different operation corners
- Arnold Combines an eFPGA from Quicklogic and a 32bit PULPissimo system with a RI5CY with FPU support
- Trikarenos PULPissimo system with triple core lockstep capability
- Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
- Honey Bunny PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.
- Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
- Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
- Mr. Wolf new generation PULP system with 1 fabric controller (micro-riscy) and a cluster with eight RI5CY (RISC-V cores optimized for DSP operations) and two shared IEEE-754 FPUs.
- GAP8 Is the commercial brother of Mr. Wolf, A PULP system with 1 fabric controller and a cluster with eight RI5CY (RISC-V cores optimized for DSP operations).
- Cerberus PULPissimo system with triple core lockstep capability
- Eclipse Eclipse is a PULPissimo system with the new FPU using the X-Interface and CV32E40P
- Kairos Kairos hosts the first silicon implementation of the RISC-V Core Local Interrupt Controller (CLIC)
- Neo Complete system around CVA6/Ariane with RPC Dram support
- Minpool Smaller scale Mempool implementation with 16 Snitch cores
- Zest PULP system with both Snitch and RI5CY cluster and the new Fenrir I/O interface
- Echoes PULPissimo system with FFT accelerator, new peripherals and for the first time CV32E40P core.
- Yun The ARA vector unit together with the CVA6 core.
- Darkside Cluster based OpenPULP implementation with several accelerators and updates to 32bit cores.
- Dustin PULP cluster with new SIMD extensions.
- Billywig multi-core system with a new Snitch core (RV32IMAFD) with extensions to improve stream processing
- Plink Serial I/O interface for PULP
- Urania BigPULP implementation with one Ariane core and two clusters each with 4x RI5CY cores and a DDR interface
- Xavier PULPissimo system with multiple SPI ports, a uDMA with pre-processing capability and a QNE accelerator
- Rosetta PULPissimo system with multiple in-memory computing accelerators.
- Scarabaeus a 64-bit system with one Ariane core, peripherals, and a new interrupt controller.
- Atomario multi-cluster system with two four-core RI5CY clusters.
- Patronus chip with three separate single RISC-V cores. It is technically a newer PULPino (single core system)
- Imperio single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project.
- Phoebe an improved version of Selene, 4 cores and 1 shared vectorial FPU using logarithmic number system
- Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 kByte memory
- Fulmine Third generation of PULP platform, Convolutional accelerator, crypto accelerator, body biasing FLLs, 256 kByte memory
- Artemis 4 core PULP system including FPU.
- Hecate 4 core PULP system with 2 shared FPUs.
- Selene 4 core PULP system with 1 shared FPU using a logarithmic number system.
- Diana 4 core PULP system with FPUs designed using approximate computing techniques.
- Vivosoc3.142 Continued updates on the 4 core mixed-signal PULP system with a low-power A/D converter
- Vivosoc3 An even more updated version of 4 core mixed-signal PULP system with a low-power A/D converter
- Vivosoc2 4 core mixed-signal PULP system with a low-power A/D converter, 128 kB L2,
- Vivosoc2.001 updated version of 4 core mixed-signal PULP system with a low-power A/D converter
- Triphos Power management IC for VivoSoC
- Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter
- Sid Large PULP chip with in-exact accelerators, LL version
- Diego Large PULP chip with in-exact accelerators, LVT version
- Manny Large PULP chip with in-exact accelerators, sub-threshold version
- Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
- Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
Templates and Logos
This archive contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.
For documentation, please use the following Word template (v1.0). And here is a PULP slide template for Powerpoint (v1.1).