PULP Freertos with LLVM
From iis-projects
Contents
Overview
Status: Available
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
Real-time systems are systems that need to guarantee certain time constraints such as for example responding within a certain time frame. This means that computations not only need to be logically correct but also the physical instant of the result computation has to meet a particular timing constraint.
Regular general-purpose operating systems such as Linux are often not designed to ensure that real-time constraints are respected.
To address that problem several so called real-time operating systems have been developed in the last decades and used in several fields where the design of safety-critical systems matters (automotive and aerospace above all).
ControlPULP is an open-source HW/SW platform based on PULP [1], a parallel embedded MCU implementing the RISC-V ISA. ControlPULP has been developed to serve as an integrated power controller for HPC processors [2]. In this scenario, a timely response from multiple MIMO interfaces is required to be able to track and set the operating point of the controlled system in a workload-aware manner.
Currently, we support FreeRTOS [5] in ControlPULP as real-time operating system using our custom compiler toolchain based on GCC [3] which supports various extension that are implemented in our cores. We also started using LLVM [6], another large popular compiler framework, in our research group.
Project
The goal of this project is to port PULP FreeRTOS so that it can also be compiled with LLVM:
- Review and study ControlPULP SystemVerilog code [4]
- (Optional) If you prefer to develop on an FPGA set up the ControlPULP FPGA flow
- Review and study PULP FreeRTOS.
- Port the project LLVM.
- Compare LLVM against GCC PULP FreeRTOS with various benchmarks. ControlPULP can be easily emulated on an FPGA (ZCU102) and can execute compiled code on it.
Character
- 15% Literature / architecture review
- 65% Software layer
- 20% Evaluation
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I
- Basic knowledge of operating systems
- Knowledge of C programming language and unix tooling as from previous bachelor/master courses
References
[1] https://github.com/pulp-platform/pulp
[2] ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
[3] https://github.com/pulp-platform/riscv-gnu-toolchain
[4] https://iis-git.ee.ethz.ch/pms/control-pulp/