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Difference between revisions of "PULPonFPGA: Hardware L2 Cache"

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===Status: Available ===
===Status: Available ===
: Looking for Interested Master Students
: Looking for 1-2 Interested Master Students (Semester Project)
: Supervision: [[:User:Vogelpi|Pirmin Vogel]], [[:User:Michscha|Michael Schaffner]], [[:User:Mandrea|Andrea Marongiu]]
: Supervision: [[:User:Vogelpi|Pirmin Vogel]], [[:User:Michscha|Michael Schaffner]], [[:User:Mandrea|Andrea Marongiu]]

Revision as of 12:44, 12 April 2016



While high-end heterogeneous systems-on-chip (SoCs) are increasingly supporting heterogeneous uniform memory access (hUMA), their low-power counterparts targeting the embedded domain still lack basic features like virtual memory support for accelerators. As opposed to simply passing virtual address pointers, explicit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.

At IIS, we study the integration of programmable many-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs [1,2]. Recently, we have switched to a new evaluation platform based on the ARM Juno Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [4] capable of implementing PULP [5] with 4 to 8 clusters and a total of 32 to 64 cores.

Short Description

The two subsystems are on two separate chips and connected through a high-bandwidth off-chip interface. To reduce the traffic on this interface, PULP can be equipped with an L2 cache memory that caches frequent accesses to the shared main memory. This also allows to reduce the stress on our lightweight virtual memory solution. While the overall platform is of considerable complexity, your job is well defined and isolated: The idea of this project is to develop the hardware IP of this L2 cache.

You can start from an existing IP block designed in a previous project. This IP is equipped with proprietary interfaces and needs to be adapted to use the widely adopted AXI4 protocol [6], which has built-in cache control signals that shall be used by your new IP. Besides designing the IP, your job is also to develop a set of testbenches to verify the functionality and analyze the design. The work primarily targets the implementation on the Xilinx Virtex-7 FPGA but if desired, an ASIC back-end design can also be implemented.

Status: Available

Looking for 1-2 Interested Master Students (Semester Project)
Supervision: Pirmin Vogel, Michael Schaffner, Andrea Marongiu


20% Theory, Algorithms and Simulation
50% VHDL, FPGA/ASIC Design
30% Verification


VHDL/System Verilog, C


Luca Benini


  1. P. Vogel, A. Marongiu, L. Benini, "Lightweight Virtual Memory Support for Many-Core Accelerators in Heterogeneous Embedded SoCs", Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'15), Amsterdam, The Netherlands, 2015. link
  2. P. Vogel, A. Marongiu, L. Benini, "Lightweight Virtual Memory Support for Zero-Copy Sharing of Pointer-Rich Data Structures in Heterogeneous Embedded SoCs", to be published, 2016.
  3. ARM Juno Development Platform link
  4. Xilinx Virtex-7 XC7V2000T FPGA link
  5. PULP link
  6. AMBA 4 AXI Protocol Specifications link
  7. D. J. Sorin, M. D. Hill, D. A. Wood, "A Primer on Memory Consistency and Cache Coherence", Morgan & Claypool Publishers, 2011. link

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