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(Created page with "thumb|600px ==Short Description== While high-end heterogeneous systems-on-chip (SoCs) are increasingly supporting heterogeneous uniform memory access...")
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===Status: Available ===
===Status: Available ===
: Looking for Interested Master Students
: Looking for Interested Master Students
: Supervision: [[:User:Vogelpi|Pirmin Vogel]], [[:User:Schaffner|Michael Schaffner]]
: Supervision: [[:User:Vogelpi|Pirmin Vogel]], [[:User:Schaffner|Michael Schaffner]], [[:User:Mandrea|Andrea Marongiu]]

Revision as of 10:07, 13 April 2015

Pulp on fpga.png

Short Description

While high-end heterogeneous systems-on-chip (SoCs) are increasingly supporting heterogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the embedded domain still lack basic features like virtual memory support for accelerators. As opposed to simply passing virtual address pointers, explicit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.

At IIS, we use an evaluation platform based on the Xilinx Zynq-7000 SoC with PULPonFPGA implemented in the programmable logic to study the integration of programmable many-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. Based on a content-addressable memory (CAM), efficiently managed by a kernel-level driver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units (IOMMUs).

The idea of this project is to enhance our solution with a multi-level TLB and lightweight hardware support for TLB management in order to support dynamic self-updating of the TLB without frequent host interaction.

This project requires work to be done at several layers of abstraction. More precisely, you will need to:

... Evaluate the cost and benefit of different alternative RAB/TLB designs (size-complexity tradeoff).
... Implement the selected design in hardware by extending the current design.
... Extend the Linux kernel-level driver managing the RAB
... Set up operation on the evaluation platform, and characterize the enhanced solution using heterogeneous benchmark applications.

Status: Available

Looking for Interested Master Students
Supervision: Pirmin Vogel, Michael Schaffner, Andrea Marongiu


40% Theory, Algorithms and Simulation
40% VHDL, FPGA Design
20% Linux Kernel-Level Driver Development


VHDL/System Verilog, C
Embedded Linux experience
Experience with Linux kernel-level driver development is of advantage.


Luca Benini


  • Xilinx Zynq-7000 All-Programmable SoC [1]
  • PULP [2]

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