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Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs

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Status: Available

  • Type: Semester Thesis
  • Professor: Prof. Dr. L. Benini
  • Supervisors:


More infos follow soon...



  • 20% Literature / architecture review
  • 20% RTL implementation
  • 40% Power Plannign & Backend Design
  • 20% Evaluation/Simulation


  • Strong interest in computer architecture and SoCs
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with ASIC implementation flow (ASIC Backend/power-planning flow) as taught in VLSI II (the project can be started in parallel to attending the VLSI2 lecture)
  • Basic Linux OS handling skills