Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
From iis-projects
Revision as of 01:03, 23 November 2021 by Meggiman (talk | contribs) (Created page with "<!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> Category:Digital Category:Energy Efficient SoCs Category:2022 Cate...")
Contents
Overview
Status: Available
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
More infos follow soon...
Project
Character
- 20% Literature / architecture review
- 20% RTL implementation
- 40% Power Plannign & Backend Design
- 20% Evaluation/Simulation
Prerequisites
- Strong interest in computer architecture and SoCs
- Experience with digital design in SystemVerilog as taught in VLSI I
- Experience with ASIC implementation flow (ASIC Backend/power-planning flow) as taught in VLSI II (the project can be started in parallel to attending the VLSI2 lecture)
- Basic Linux OS handling skills