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Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs

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Status: In Progress

  • Type: Semester Thesis
  • Professor: Prof. Dr. L. Benini
  • Supervisors:


The Parallel Ultra Low Power (PULP) Platform started as a joint effort between the Integrated Systems Laboratory (IIS) of ETH Zürich and Energy-efficient Embedded Systems (EEES) group of the University of Bologna in 2013 to explore new and efficient architectures for ultra-low-power processing. Its\u2019 aim is the development of an open, scalable hardware and software research and development platform with the goal to break the energy efficiency barrier within a power envelope of a few milliwatts, as well as satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays and vital signs monitors.

Amongst the tooling, sofware development kits and a rich ecosystem of reusable digital hardware IPs like several RISC-V cores, the project consists of several reference PULP SoC architectures that act as research verhicle for novel low-power design methodologies and have been silicon proven in several tapeouts in various advanced technology nodes (Flamand et al. 2018; Pullini et al. 2019; Rossi et al. 2022). The PULPissimo SoC architecture is the single-core microcontroller variant that combines an energy efficient 5-stage single-issue in-order RV32IMC RISC-V core (Gautschi et al. 2017) with common microcontroller peripherals like UART, SPI, I2C or MIPI CPI camera interface. Those peripherals are attaches to a lightweight configurable DMA that allows the peripherals to independently fetch microcode instructions, read TX data or store received data from chip-external components (Pullini et al. 2017). However, interaction between peripherals (e.g. timer-triggered UART transaction or reactive SPI transaction on a GPIO toggle) still requires intervention of the RISC-V core; The traditional modus-operandi of a microntroller in aformentioned scenarios is to be triggered by the target event through an interrupt and trigger the desired action within a separate peripheral as part of the interrupt service routine (ISR). This traditional approach has several drawbacks:

  • The reaction time between event and the action trigger is limited by the execution of the ISR. The core has to wake-up from deep-sleep, save the context before jumping to the interrupt vector table before executing the actual ISR that triggers the action through writes to memory-mapped configuration registers of the peripheral.
  • Power-gating opportunities are limited due to the necessity to retain major parts of the main system memory due to the use of static random access memory (SRAM) for code execution and data storage.

The popular nRF52 Bluetooth low-energy microcontroller family from Nordic Semiconductor contains a system that allow hardware based linking of peripheral events to peripheral tasks without intervention of the CPU core based on event lookup tables and a multiplexing task triggering interconnects (Elahi et al. 2015).

The aim of this project is to develop a solution for the PULP platform with similar capabilities however based on an entirely different hardware approach; The Peripheral event linking (PEL) subsystem shall be completely parametric in the number of event sources and peripheral agnostic i.e. does not require any modification to existing peripherals for integration. Furthermore the IP should leverage the existing SoC interconnect for communication with the peripheral and the existing interrupt control infrastructure for the event triggering mechanism. Finally, the IP shall be integrated and verified within the PULPissimo SoC architecture to evaluate the relevant performance metrics using the PEL subsystem for common microcontroller applications.


Project Description

Task I: Getting familiar with the PULPissimo SoC and PULP Hardware IP Ecosystem

In this phase you will dive into the world of the PULP platform and familiarize yourself with the source code of the PULPissimo SoC. Familiarity with the PULP IP portfolio is a key milestone that will significantly speed up the RTL development of [sec:task-ii:-development] due to increased IP reuse.

  • Get familiar with PULPissimo architecture in particular the SoC interconnect and the interrupt system.
  • Go through RTL code of PULP AXI IP to learn about coding best practices and to become familiar of reusable common_cells IPs.
  • Become familiar with IP dependency management tool Bender and setup the simulation environment for standalone PEL IP simulation and system-level simulation as part of PULPissimo.
  • Come up with and specify one or several possible hardware architectures for the PEL subsystem with an analysis of advantages and drawbacks of each alternative architecture.

Task II: Development of the PEL IP and Integration in PULPissimo

After deciding on the most suitable architecture for the PEL system and specification of features, parametrization and configuration options, the next step consists of developing and standalone-verification of the RTL in SystemVerilog. In the second step of this task you will integrate your IP into the PULPissimo SoC and simulate its behavior in the system-level context.

  • Implement the specified architecture in SystemVerilog following the lowRISC Verilog Coding Style Guide (lowRISC 2021).
  • Verify the RTL code standalone using SystemVerilog test-benches.
  • Integrate PEL-subsystem into PULPissimo
  • Simulate and verify integration by extending the existing PULPissimo verification infrastructure.

Task III: Performance Evaluation

In the final part of your thesis, you will evaluate key metrics like silicon-area, event linking latency, real-time properties (e.g. determinism of the latency) and potential energy savings using the existing simulation environments. The goal of this task is to assess the benefits of the new PEL system and provide some indication under which scenarios its use is beneficial compared to the traditional interrupt based techniques.

  • Synthesis of the PEL IP to estimate silicon area impact.
  • Evaluation of event linking latency using simulation.
  • Energy saving estimation using existing power models for PULP and simulation data of common microcontroller applications.

Task IV (optional): Potential Additional Task Items

These points are optional, but may be very useful.

  • Development of C driver for the new IP
  • Integration of PEL-system with co-developed (different student thesis) power management unit
  • Post-layout power simulation in TSMC65nm technology


  • 20% Literature / architecture review
  • 20% RTL implementation
  • 40% Power Plannign & Backend Design
  • 20% Evaluation/Simulation


  • Strong interest in computer architecture and SoCs
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with ASIC implementation flow (ASIC Backend/power-planning flow) as taught in VLSI II (the project can be started in parallel to attending the VLSI2 lecture)
  • Basic Linux OS handling skills