Pirmin Vogel received his M.Sc. degree from the Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland, where he is currently pursuing the Ph.D. degree. Since 2013, he has been a research assistant with the Integrated Systems Laboratory at ETHZ. His research interests include digital signal processing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparent accelerator programming.
Projects in Progress
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- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- Securing Block Ciphers against SCA and SIFA
- Ibex: FPGA Optimizations
- Ibex: Bit-Manipulation Extension
- HERO: TLB Invalidation
- BigPULP: Shared Virtual Memory Multicluster Extensions
- BigPULP: Multicluster Synchronization Extensions
- Smart Virtual Memory Sharing
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- Baseband Meets CPU
- Eﬃcient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems