Difference between revisions of "Probing the limits of fake-quantised neural networks"
From iis-projects
| Line 1: | Line 1: | ||
| − | ==Introduction== | + | == Introduction == |
Abstract of the project | Abstract of the project | ||
| − | |||
| − | + | == Project description == | |
| − | |||
| − | + | == Competences == | |
Required: | Required: | ||
| Line 22: | Line 20: | ||
| − | + | == Character == | |
: 20% Theory | : 20% Theory | ||
| Line 29: | Line 27: | ||
| − | + | == Professor == | |
: [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] | : [http://www.iis.ee.ethz.ch/people/person-detail.html?persid=194234 Luca Benini] | ||
| − | === | + | ===== Status: Available ===== |
| − | * '''[[Project Plan]]''' | + | We are looking for 1 Master student. |
| − | * '''[[Project Meetings]]''' | + | It is possible to complete the project either as a Semester Project or a Master Thesis. |
| − | * '''[[Design Review]]''' | + | Supervisors: [[:User:spmatteo | Matteo Spallanzani]][mailto:spmatteo@iis.ee.ethz.ch spmatteo@iis.ee.ethz.ch], [[:User:andrire | Renzo Andri (Huawei RC Zurich)]] |
| − | * '''[[Coding Guidelines]]''' | + | |
| − | * '''[[Final Report]]''' | + | |
| − | * '''[[Final Presentation]]''' | + | === Logistics === |
| + | |||
| + | === Further details === | ||
| + | |||
| + | <!-- * '''[[Project Plan]]''' ---> | ||
| + | <!-- * '''[[Project Meetings]]''' ---> | ||
| + | <!-- * '''[[Design Review]]''' ---> | ||
| + | <!-- * '''[[Coding Guidelines]]''' ---> | ||
| + | <!-- * '''[[Final Report]]''' ---> | ||
| + | <!-- * '''[[Final Presentation]]''' ---> | ||
| Line 55: | Line 62: | ||
[[Category:cat4]] | [[Category:cat4]] | ||
[[Category:cat5]] | [[Category:cat5]] | ||
| − | |||
[[Category:Digital]] | [[Category:Digital]] | ||
| − | |||
| − | |||
[[Category:Computer Architecture]] | [[Category:Computer Architecture]] | ||
[[Category:Acceleration and Transprecision]] | [[Category:Acceleration and Transprecision]] | ||
| Line 78: | Line 82: | ||
[[Category:EmbeddedAI]] | [[Category:EmbeddedAI]] | ||
| − | + | [[Category:ASIC]] | |
| − | + | [[Category:FPGA]] | |
| − | |||
| − | + | [[Category:System Design]] | |
| − | + | [[Category:Processor]] | |
| − | + | [[Category:Telecommunications]] | |
| − | + | [[Category:Modelling]] | |
| − | + | [[Category:Software]] | |
| − | + | [[Category:Audio]] | |
[[Category:Analog]] | [[Category:Analog]] | ||
| + | |||
[[Category:Nano-TCAD]] | [[Category:Nano-TCAD]] | ||
[[Category:AnalogInt]] | [[Category:AnalogInt]] | ||
| − | + | [[Category:Telecommunications]] | |
| − | |||
| − | |||
STATUS | STATUS | ||
| + | [[Category:Hot]] | ||
[[Category:Available]] | [[Category:Available]] | ||
[[Category:In progress]] | [[Category:In progress]] | ||
[[Category:Completed]] | [[Category:Completed]] | ||
| − | |||
TYPE OF WORK | TYPE OF WORK | ||
| Line 123: | Line 125: | ||
[[Category:EPI]] | [[Category:EPI]] | ||
[[Category:Fractal]] | [[Category:Fractal]] | ||
| − | |||
YEAR (IF FINISHED) | YEAR (IF FINISHED) | ||
| Line 143: | Line 144: | ||
[[Category:Deep Learning Projects]] | [[Category:Deep Learning Projects]] | ||
[[Category:Deep Learning Acceleration]] | [[Category:Deep Learning Acceleration]] | ||
| + | [[Category:Available]] | ||
[[Category:Semester Thesis]] | [[Category:Semester Thesis]] | ||
[[Category:Master Thesis]] | [[Category:Master Thesis]] | ||
[[Category:Hot]] | [[Category:Hot]] | ||
| − | [[Category: | + | [[Category:spmatteo]] |
| − | [[Category: | + | [[Category:andrire]] |
| − | |||
Revision as of 20:37, 24 September 2021
Contents
Introduction
Abstract of the project
Project description
Competences
Required:
- Numerical representation formats (integer, floating-point)
- Numerical analysis
- Python programming
- C/C++ programming
Optional:
- Knowledge of the PyTorch deep learning framework
- Knowledge of digital arithmetic (e.g., two's complement, overflow, wraparound)
Character
- 20% Theory
- 40% C/C++ and Python coding
- 40% Deep learning
Professor
Status: Available
We are looking for 1 Master student. It is possible to complete the project either as a Semester Project or a Master Thesis. Supervisors: Matteo Spallanzanispmatteo@iis.ee.ethz.ch, Renzo Andri (Huawei RC Zurich)
