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RISC-V base ISA for ultra-low-area cores (2-3G) - Revision history
2024-03-29T12:51:05Z
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http://iis-projects.ee.ethz.ch/index.php?title=RISC-V_base_ISA_for_ultra-low-area_cores_(2-3G)&diff=7108&oldid=prev
Tbenz at 11:15, 15 November 2021
2021-11-15T11:15:35Z
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 11:15, 15 November 2021</td>
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Tbenz
http://iis-projects.ee.ethz.ch/index.php?title=RISC-V_base_ISA_for_ultra-low-area_cores_(2-3G)&diff=5879&oldid=prev
Tbenz: Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Group Project Category:Paulsc Category:Tbenz Category:Available == Introduc..."
2020-11-11T10:31:15Z
<p>Created page with "<a href="/index.php?title=Category:Digital" class="mw-redirect" title="Category:Digital">Category:Digital</a> <a href="/index.php?title=Category:High_Performance_SoCs" class="mw-redirect" title="Category:High Performance SoCs">Category:High Performance SoCs</a> <a href="/index.php?title=Category:2020" title="Category:2020">Category:2020</a> <a href="/index.php?title=Category:Group_Project" title="Category:Group Project">Category:Group Project</a> <a href="/index.php?title=Category:Paulsc" class="mw-redirect" title="Category:Paulsc">Category:Paulsc</a> <a href="/index.php?title=Category:Tbenz" class="mw-redirect" title="Category:Tbenz">Category:Tbenz</a> <a href="/index.php?title=Category:Available" title="Category:Available">Category:Available</a> == Introduc..."</p>
<p><b>New page</b></p><div>[[Category:Digital]]<br />
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<br />
== Introduction ==<br />
At IIS we have developed the Snitch core, a small RISC-V core which only consists of around 20’000 Gates. In our research we keep finding opportunities to replace hard coded finite state machines (FSMs) in our SoCs with a Snitch core. Doing so allows us, amongst other things, to fix critical bugs in our systems even after tapeout by firmware updates. <br />
<br />
The RISC-V foundation currently specifies two ''32 bit base ISA'' types:<br />
* '''RV32I (Integer)''' which specifies 32 ''32 bit integer registers''<br />
* '''RV32E (Embedded)''' which specifies 16 ''32 bit integer registers''<br />
<br />
In many applications, where we could replace a FSM with a Snitch core, the resulting code will be so simple that even 16 registers would be too many. As most of the area of the Snitch is used by the register file, cutting down the numbers of registers will yield a massive reduction in the cores area. We therefore propose a new type of base ISA for ultra-small embedded cores: '''RV32N (Nano)''' which only specifies 8 ''32 bit registers''. <br />
<br />
== Project Content ==<br />
The project can be divided in the following sub tasks:<br />
<br />
* Create the RV32N base ISA specification (base it on the RV32I & RV32E specifications found in the RISC-V ISA Manual)<br />
* Modify the Snitch core according to your RV32N specification<br />
* Evaluate the area savings from RV32N over RV32I & RV32E<br />
* ''Stretch goal:'' Identify additional area saving opportunities and adapt both the RV32N and the Snitch core accordingly<br />
* ''Stretch goal:'' modify LLVM to support RV32N<br />
<br />
== Prerequisites ==<br />
* Interest in computer architecture<br />
* Preferably: Experience with HDLs as taught in ''VLSI I''<br />
<br />
==Composition==<br />
* 20% RV32N specification<br />
* 30% Writing RTL code <br />
* 30% Evaluation<br />
* 20% RTL optimization<br />
<br />
== Further Reading ==<br />
* [https://riscv.org//wp-content/uploads/2017/05/riscv-spec-v2.2.pdf RISC-V ISA Manual]<br />
<br />
== Project Supervisors ==<br />
* [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]<br />
* [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]</div>
Tbenz