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RISC-V base ISA for ultra-low-area cores (2-3G)

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Introduction

At IIS we have developed the Snitch core, a small RISC-V core which only consists of around 20’000 Gates. In our research we keep finding opportunities to replace hard coded finite state machines (FSMs) in our SoCs with a Snitch core. Doing so allows us, amongst other things, to fix critical bugs in our systems even after tapeout by firmware updates.

The RISC-V foundation currently specifies two 32 bit base ISA types:

  • RV32I (Integer) which specifies 32 32 bit integer registers
  • RV32E (Embedded) which specifies 16 32 bit integer registers

In many applications, where we could replace a FSM with a Snitch core, the resulting code will be so simple that even 16 registers would be too many. As most of the area of the Snitch is used by the register file, cutting down the numbers of registers will yield a massive reduction in the cores area. We therefore propose a new type of base ISA for ultra-small embedded cores: RV32N (Nano) which only specifies 8 32 bit registers.

Project Content

The project can be divided in the following sub tasks:

  • Create the RV32N base ISA specification (base it on the RV32I & RV32E specifications found in the RISC-V ISA Manual)
  • Modify the Snitch core according to your RV32N specification
  • Evaluate the area savings from RV32N over RV32I & RV32E
  • Stretch goal: Identify additional area saving opportunities and adapt both the RV32N and the Snitch core accordingly
  • Stretch goal: modify LLVM to support RV32N

Prerequisites

  • Interest in computer architecture
  • Preferably: Experience with HDLs as taught in VLSI I

Composition

  • 20% RV32N specification
  • 30% Writing RTL code
  • 30% Evaluation
  • 20% RTL optimization

Further Reading

Project Supervisors