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===Status: Available ===
===Status: Available ===
: Supervision: [[:User:Adimauro | Alfio Di Mauro]] Dr. C. Martelli (3db Access AG), Dr. Boris Danev (3db Access AG)
: Supervision: [[:User:Adimauro | Alfio Di Mauro]], Dr. C. Martelli (3db Access AG), Dr. Boris Danev (3db Access AG)

Revision as of 12:09, 29 June 2020


Ultra-Wideband has been recently reported by EETimes as one of the main pivotal events in IoT in 2019 [5 Pivotal Events in IoT and Embedded]. After Apple quietly introduced the U1 chipset in its high-end iPhone 11, Volkswagen, the largest automaker, also unveiled first models using UWB for car access: the ID.3 and the Golf 8 [Dazwischengefunkt: Über serienmäßige Sicherheitslücken]. As reported recently on the blog of 3db-Access AG (VW Adopts UWB for Secure Car Access), the FCC certification number of the ID.3 key fob indicates that VW is implementing the Low-Rate Pulse (LRP) UWB technology. By introducing this technology in a classical key fob, VW demonstrates the feasibility of an ultra-low-power, low-cost, provably secure, high link budget (communication range) and automotive-qualified wireless ranging device simply powered from a small coin-cell battery: a technical achievement that was simply not possible a few years ago. As a pioneer in secure wireless access [Chip einer Schweizer Firma soll vor Relay-Attacken schützen], 3db Access and its partners will continue to promote UWB and will further push this technology to unprecedented performances. The new IEEE Standard 802.15.4z describes two kinds of physical layers (PHY), Low-Rate Pulse (LRP) and the High-Rate Pulse (HPR). The LRP UWB technology from 3db-Access AG is today on the road, especially because it is accurate and provably secure, both aspects which are of fundamental importance for the automotive industry. The IEEE 802.15.4z standard will be released in July 2020 and contains unique PHY and MAC layer features to achieve secure ranging. Such secure ranging procedures require a microcontroller core on-chip and a set of security functions including secure storage, key generation, key exchange, encryption/decryption, random number generation, etc. Risc-V [The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2] is a very promising microcontroller core to realize and promoting open-source secure ranging as defined in the IEEE 802.15.4z standard. In order to build a large, continuing community of users and therefore accumulate designs and software, the Risc-V ISA designers support a wide variety of practical uses: small, fast, and low-power real-world implementations, without over-architecting it for a particular application. The instruction set is the main interface in a computer because it lies between the hardware and the software. If a good instruction set was open, available for use by all, it should dramatically reduce the cost of software by permitting far more reuse. It should also increase competition among hardware providers, who can use more resources for design and less for software support. A well-designed open instruction set, based on well-established principles should attract long-term support by many vendors.

Project description

The target of this Master Thesis is to develop a RISC-V based secure ranging using IEEE 802.15.4z MAC layer and the already available 3db UWB IC. For this thesis, the RISC-V component will be off-the-shelf and connected via a SPI interface to the 3db UWB IC. During this thesis, the student will gain expertise in the new UWB standard and RISC-V programming for the purposes of secure and highly precise ranging based on UWB LRP PHY. Performance evaluation will be carried on and compared among several approaches.


The project will be split up three phases, as described below:

Phase 1

1. Get familiar with the already existing LPR UWB as described on the IEEE Standard 802.15.4z.

2. Study the MAC layer secure ranging procedures in the IEEE 802.15.4z and elaborate the security requirements for the RISC-V core.

3. Integrate the RISC-V on chip together with 3db Access AG to make a proof-of-technology.

Phase 2

1. Implement secure ranging based on timestamps and secure exchange of timestamps.

2. Evaluate the performance of the secure ranging on RISC-V.

3. Propose procedures for optimized multi-node secure ranging.

Phase 3

1. Finalize the performance evaluation.

2. Write the thesis and prepare presentation.


By the end of Phase 1 the following should be completed:

  • Requirements and implementation plan.

By the end of Phase 2 the following should be completed:

  • Secure ranging demo and performance evaluation.

By the end of Phase 3 the following should be completed:

  • Final Presentation.
  • Master Thesis Document.

Status: Available

Supervision: Alfio Di Mauro, Dr. C. Martelli (3db Access AG), Dr. Boris Danev (3db Access AG)


Prof. Dr. Luca Benini, Prof. Dr. Srdjan Capkun


Required Skills

To work on this project, you will need:

  • Knowledge of an embedded programming language is necessary.
  • Familiarity with Risc-V architecture and tool-chains is a plus.

Project Organization

Weekly meeting

The student shall meet with the advisor(s) every week in order to discuss any issue/problems that may have persisted during the previous week and to coordinate the next steps. These meetings are meant to provide a guaranteed timeslot for mutual exchange of information on how to proceed, clear out any questions from either side and to ensure the student’s progress.

Weekly report

There will be a weekly report sent by the student at the end of every week. The main purpose of this report is to document the project’s progress and should be used by the student as a way to communicate any problems that arise during the week. The report, along with all other relevant documents (source code, datasheets, papers, etc), should be updated regularly to the assigned SVN account.

Final report

PDF copies of the report and presentation, as well as the developed software, build script/project files, drawings/illustrations, acquired data, etc. needs to be handed in at the end of the project.

Final presentation

At the end of the project, the outcome of the thesis will be presented in a 20 minutes talk and 5 minutes of discussion in front of interested people of the Integrated Systems Laboratory. The presentation is open to the public, so you are welcome to invite interested friends.


The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [1]

The IIS/DZ coding guidelines [2]

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