Radiation Testing of a PULP ASIC

Overview

Status: Available

• Type: Semester Thesis
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Michael Rogenmoser: michaero@iis.ee.ethz.ch
  • Frank Gurkaynak: kgf@iis.ee.ethz.ch

Introduction

At IIS, we recently taped out two ASICs with features for fault tolerance, increasing redundancy to radiation-induced errors, e.g. for Space applications.

After these Chips (Cerberus and Trikarenos) are brought up once they return from being manufactured, we would like to test them under a radiation beam.

Project

In this project, an independent testing infrastructure for the two chips will be developed, allowing for testing in a sealed chamber under a radiation beam. As this chamber only provides limited access, a reliable stand-alone infrastructure is required. This includes:

• An overall test setup, picking the devices to control and interface with the chips
• software for a simple computer to reliably control and program the chip, and log any errors
• Time-permitting, a PCB for the chips, providing power and clock and interface options

As the chips are not back from manufacturing yet, the testing infrastructure will initially be deployed with an FPGA port of the chip for debugging.

Character

• 30% System design
• 50% Software design (scripting, C, python)
• 20% PCB design

Prerequisites

• Familiarity with ASIC design and testing is beneficial
• Experience with PCB design is beneficial