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Real-time Linux on RISC-V

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Overview

Status: In Progress

Introduction

Preempt-rt-logo.png

Linux[1] is a monolithic, modular, Unix-like, open-source general-purpose kernel running on servers, workstations, mobile devices and embedded systems.

Currently, mainline Linux is not suitable for real-time workloads which require a deterministic and predictable behavior. Many design decision rather focus on throughput. There have been various approaches trying to address problem such as RTLinux[4], Xenomai[5] and PREEMPT_RT [2][11]. This work will focus on PREEMPT_RT.

PREEMPT_RT is a set of patches for Linux to turn into a kernel that is more suitable for real-time applications. These changes try to minimize the amount of kernel code that is non-preemptible which translates directly into a more reactive system. The core algorithms and data structures that are changed are the timer, interrupt handlers, RCU, mutexes and spinlocks[3][6].

As a development platform we will use Cheshire[7], an open-source SoC from our group that features a 64-bit RISC-V core and various peripherals such as UART, SPI, I2C, VGA and more.

Project

The goal of this project is to port PREEMPT_RT Linux to run on 64-bit RISC-V Linux, evaluate performance compare to baseline Linux and propose modifications. As development environment you will run Cheshire on a FPGA.

  • Port PREEMPT_RT Linux to Cheshire
  • Evaluate Performance compare to other configuration such as baseline Linux, Sel4 and Hypervisor configurations (Bao[8], Sel4 VMM[9]). You can start from e.g. just running cyclitest[10].
  • Propose modifications to Hardware and Software. This will depend on the scope of the thesis (SA or MA). For example, support for the Core-Local Interrupt Controller[12] could be added.

Character

  • 10% Literature / architecture review
  • 60% C programming
  • 10% RTL design
  • 20% Evaluation

Prerequisites

  • Good knowledge of operating systems
  • Good knowledge of C programming language and UNIX tooling as from previous bachelor/master courses
  • SystemVerilog knowledge is helpful as taught in VLSI I

References

[1] https://www.kernel.org/

[2] https://wiki.linuxfoundation.org/realtime/start

[3] https://lwn.net/Articles/146861/

[4] https://www.yodaiken.com/papers/rtlmanifesto.pdf

[5] https://source.denx.de/Xenomai/xenomai/-/wikis/home

[6] https://wiki.linuxfoundation.org/realtime/documentation/technical_details/start

[7] https://github.com/pulp-platform/cheshire

[8] https://github.com/bao-project/bao-hypervisor

[9] https://sel4.systems/

[10] https://wiki.linuxfoundation.org/realtime/documentation/howto/tools/cyclictest/start

[11] https://dl.acm.org/doi/pdf/10.1145/3297714

[12] https://github.com/pulp-platform/clic