Difference between revisions of "Receiver design for the DigRF 4G high speed serial link"
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Latest revision as of 17:37, 21 December 2017
Contents
Short Description
Modern wireless receivers achieve a very high throughput. Therefore the raw sampled data from the receiver ASIC that needs to be transmitted to the following baseband ASIC can reach orders of 1 Gb/s. To avoid any disturbances to the vulnerable receiver and to mimize the number of required pins, this data is transmitted over a high speed serial link using differential signalling and a low signal amplitude.
The task of this project is to design the receiver front-end architecture of a serial DigRF4G link. This standard defines a serial link running at up to 3 Gb/s designed specifically for the interface between a receiver IC and a baseband IC.
Status: Available
- Looking for 1-2 Semester/Master students
- Contact: Benjamin Sporrer
Prerequisites
- Analog Integrated Circuits
- Communication Electronics (recommended)
Character
- 40% Theory
- 60% Mixed-Signal ASIC Design
