Difference between revisions of "Reconfigurability of SHA-3 candidates"
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In December 2010, the 5 finalists of the SHA-3 competition were announced. The SHA-3 candidates all need to provide a 256-Bit and a 512-Bit mode. The goal of this project is to implement for each of these candidates a reconfigurable core that is capable of calculating 256-Bit and 512-Bit hashes with the same hardware. | In December 2010, the 5 finalists of the SHA-3 competition were announced. The SHA-3 candidates all need to provide a 256-Bit and a 512-Bit mode. The goal of this project is to implement for each of these candidates a reconfigurable core that is capable of calculating 256-Bit and 512-Bit hashes with the same hardware. | ||
| − | ===Status: | + | ===Status: Outdated === |
: Looking for 1-2 Semester/Master students | : Looking for 1-2 Semester/Master students | ||
: Contact: [[:User:Chrikell | Christoph Keller]] | : Contact: [[:User:Chrikell | Christoph Keller]] | ||
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[[Category:Digital]] | [[Category:Digital]] | ||
| − | [[Category: | + | [[Category:Completed]] |
[[Category:Semester Thesis]] | [[Category:Semester Thesis]] | ||
Latest revision as of 14:11, 13 March 2014
Contents
Short Description
In December 2010, the 5 finalists of the SHA-3 competition were announced. The SHA-3 candidates all need to provide a 256-Bit and a 512-Bit mode. The goal of this project is to implement for each of these candidates a reconfigurable core that is capable of calculating 256-Bit and 512-Bit hashes with the same hardware.
Status: Outdated
- Looking for 1-2 Semester/Master students
- Contact: Christoph Keller
Prerequisities
- VLSI I
- Interest in Cryptography
Character
- 20% Theory
- 55% VHDL Design
- 25% ASIC Implementation
