Resource Partitioning of Caches
- Type: Bachelor or Semester Thesis
- Professor: Prof. Dr. L. Benini
We are moving towards more predictable application-class cores. Our in-house designed Ariane  (CVA6) RISC-V 64-bit core is Linux capable and features L1 data and instruction caches. On a system integration level we also have a last-level cache (LLC) . The strategy we are using is to make the whole system more predictable is resource partitioning. Specifically, partitioning the caches allows multiple processes or operating systems (through a hypervisor) to share the same caches with guaranteed worst-case performance.
The goal of the project is to investigate and implement resource partitioning schemes for caches and make them controllable through a high-level framework following the idea of Arm MPAM . There are various known schemes such as randomization, cache-coloring and temporal partitioning that can serve as starting point.
- Get familiar with cache and the controller design
- Study existing resource partitioning techniques
- Implement and verify on FPGA
- Benchmark results
- 20% Literature Review
- 60% Hardware Design
- 20% Verification and Bechmarking
- Strong interest in computer architecture and memory systems
- Experience with digital design in SystemVerilog as taught in VLSI I
- Preferred: Knowledge or experience with AXI and RISC-V