Difference between revisions of "Resource Partitioning of Caches"
From iis-projects
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<div> [2] “Supporting Temporal and Spatial Isolation in a Hypervisor for ARM Multicore Platforms” https://retis.sssup.it/~a.biondi/papers/isol-ICIT18.pdf </div> | <div> [2] “Supporting Temporal and Spatial Isolation in a Hypervisor for ARM Multicore Platforms” https://retis.sssup.it/~a.biondi/papers/isol-ICIT18.pdf </div> | ||
<div> [3] “CVA6” https://github.com/pulp-platform/cva6 </div> | <div> [3] “CVA6” https://github.com/pulp-platform/cva6 </div> | ||
+ | <div> [4] ”Last-level cache (LLC)” https://github.com/pulp-platform/axi_llc</div> |
Revision as of 12:16, 15 November 2022
Contents
Overview
Status: Available
- Type: Bachelor or Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
We are moving towards more predictable application-class cores. Our in-house designed Ariane [3] (CVA6) RISC-V 64-bit core is Linux capable and features L1 data and instruction caches. On a system integration level we also have a last-level cache (LLC) [4]. The strategy we are using is to make the whole system more predictable is resource partitioning. Specifically, partitioning the caches allows multiple processes or operating systems (through a hypervisor) to share the same caches with guaranteed worst-case performance.
Project
The goal of the project is to investigate and implement resource partitioning schemes for caches and make them controllable through a high-level framework following the idea of Arm MPAM [2]. There are various known schemes such as randomization, cache-coloring and temporal partitioning[1] that can serve as starting point.
- Get familiar with cache and the controller design
- Study existing resource partitioning techniques
- Implement and verify on FPGA
- Benchmark results
Character
- 20% Literature Review
- 60% Hardware Design
- 20% Verification and Bechmarking
Prerequisites
- Strong interest in computer architecture and memory systems
- Experience with digital design in SystemVerilog as taught in VLSI I
- Preferred: Knowledge or experience with AXI and RISC-V