Difference between revisions of "Resource Partitioning of RPC DRAM"
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= Overview = | = Overview = | ||
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* Supervisors: | * Supervisors: | ||
** [[:User:Balasr | Robert Balas]]: [mailto:balasr@iis.ee.ethz.ch balasr@iis.ee.ethz.ch] | ** [[:User:Balasr | Robert Balas]]: [mailto:balasr@iis.ee.ethz.ch balasr@iis.ee.ethz.ch] | ||
| + | ** [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch] | ||
| + | ** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch] | ||
** [[:User:Aottaviano | Alessandro Ottaviano]]: [mailto:aottaviano@iis.ee.ethz.ch aottaviano@iis.ee.ethz.ch] | ** [[:User:Aottaviano | Alessandro Ottaviano]]: [mailto:aottaviano@iis.ee.ethz.ch aottaviano@iis.ee.ethz.ch] | ||
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= Introduction = | = Introduction = | ||
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Recently, a new class of off-chip memories hit the market, targeting low area and low pin-count FPGAs and ASICs. These reduced pin count DDR (RPC DDR) [1] memories only require a simple on-chip PHY and can operate with regular digital IO pads making them usable on our ASICs. | Recently, a new class of off-chip memories hit the market, targeting low area and low pin-count FPGAs and ASICs. These reduced pin count DDR (RPC DDR) [1] memories only require a simple on-chip PHY and can operate with regular digital IO pads making them usable on our ASICs. | ||
In previous projects, we implemented a memory-controller for RPC DRAM and taped it out on two different chips [2][3]. | In previous projects, we implemented a memory-controller for RPC DRAM and taped it out on two different chips [2][3]. | ||
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| + | [[File:Rpc_dram.png|thumb|350px|]] | ||
= Project = | = Project = | ||
| − | The goal of the project is to investigate and implement resource partitioning schemes [4] in the memory-controller to improve predicatability of memory accesses. The memory controller is part of a larger platform hosting a linux capable RISC-V 64-bit core. | + | The goal of the project is to investigate and implement resource partitioning schemes [4] in the memory-controller to improve predicatability of memory accesses. For example, Arm Memory System Resource Partitioning and Monitoring (MPAM)[5] is a recent example of such a scheme. The memory controller is part of a larger platform hosting a linux capable RISC-V 64-bit core. |
* Get familiar with RPC DRAM protocol and the controller design | * Get familiar with RPC DRAM protocol and the controller design | ||
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<div> [3] http://asic.ethz.ch/2021/Dogeram.html </div> | <div> [3] http://asic.ethz.ch/2021/Dogeram.html </div> | ||
<div> [4] “Supporting Temporal and Spatial Isolation in a Hypervisor for ARM Multicore Platforms” https://retis.sssup.it/~a.biondi/papers/isol-ICIT18.pdf </div> | <div> [4] “Supporting Temporal and Spatial Isolation in a Hypervisor for ARM Multicore Platforms” https://retis.sssup.it/~a.biondi/papers/isol-ICIT18.pdf </div> | ||
| + | <div> [5] “Arm Memory System Resource Partitioning and Monitoring (MPAM)” https://developer.arm.com/documentation/ddi0598/latest </div> | ||
Revision as of 12:05, 15 November 2022
Contents
Overview
Status: Available
- Type: Bachelor or Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
Recently, a new class of off-chip memories hit the market, targeting low area and low pin-count FPGAs and ASICs. These reduced pin count DDR (RPC DDR) [1] memories only require a simple on-chip PHY and can operate with regular digital IO pads making them usable on our ASICs.
In previous projects, we implemented a memory-controller for RPC DRAM and taped it out on two different chips [2][3].
Project
The goal of the project is to investigate and implement resource partitioning schemes [4] in the memory-controller to improve predicatability of memory accesses. For example, Arm Memory System Resource Partitioning and Monitoring (MPAM)[5] is a recent example of such a scheme. The memory controller is part of a larger platform hosting a linux capable RISC-V 64-bit core.
- Get familiar with RPC DRAM protocol and the controller design
- Study existing resource partitioning techniques
- Implement and verify on FPGA
- Benchmark results
Character
- 20% Literature Review
- 60% Hardware Design
- 20% Verification and Bechmarking
Prerequisites
- Strong interest in computer architecture and memory systems
- Experience with digital design in SystemVerilog as taught in VLSI I
- Preferred: Knowledge or experience with AXI and RISC-V
References
[1] “Etron Technology Inc. RPC DRAM.” https://etronamerica.com/products/rpc-dram/
[4] “Supporting Temporal and Spatial Isolation in a Hypervisor for ARM Multicore Platforms” https://retis.sssup.it/~a.biondi/papers/isol-ICIT18.pdf
[5] “Arm Memory System Resource Partitioning and Monitoring (MPAM)” https://developer.arm.com/documentation/ddi0598/latest
