Personal tools

Difference between revisions of "SCMI Support for Power Controller Subsystem"

From iis-projects

Jump to: navigation, search
Line 11: Line 11:
[[Category:In Progress]]
= Overview =
= Overview =
== Status: Available ==
== Status: In Progress ==
* Type: Semester Thesis
* Type: Semester Thesis

Revision as of 14:15, 5 August 2022


Status: In Progress


Today’s High Performance Computing (HPC) systems are complex architectures requiring on-chip dedicated HW resources, namely Power Control Subsystems (PCS), to dynamically control the power consumption with short time constants, to prevent thermal hazards (thermal capping) and to meet the overall power budget (power capping) while interacting with external management interfaces like OS. In ARM based SoCs the PCS (System Control Processor, SCP) interacts with the OS via the System Control and Management Interface (SCMI) protocol [1], which provides a set of OS-agnostic standard SW and HW interfaces [2] for power domain, voltage, clock and sensor management through a shared mailbox system with the PCS.


ControlPULP is a RISC-V PCS platform developed at IIS and based on PULP [3] [4] [5] which relies on FreeRTOS [6] [7] to implement a Power Control Firmware (PCF) [8] routine. ControlPULP has a lightweight support for SCMI-based interaction. This means either a lightweight testbench environment in HW and lightweight protocol support in SW.

The goal of this project is to extend the actual SCMI support leveraging both HW and SW interfaces:

  • Get to know the protocol by reading the SCMI specification document [1]
  • Extend the RTL testbench setup to be specification-compliant and a stable verification environment;
  • Implement and test a selected subset of the SCMI protocol functions in SW and integrate them as a PCF [8] library.
  • Stretch goal: ControlPULP comes with an FPGA implementation on Xilinx ZCU102, where the PCS design can be controlled from an embedded Linux environment on the board. Implement mailbox-based SCMI mechanism on the FPGA platform (to be discussed for fine-grained planning).


  • 20% Literature / architecture review
  • 10% RTL
  • 60% Low-level C programming
  • 10% Evaluation


  • Experience with C programming
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with FPGA mapping as taught in VLSI I


[1] Arm System Control and Management Interface

[2] ARM SCP Firmware

[3] Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

[4] Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

[5] PULP (GitHub repository)

[6] FreeRTOS

[7] FreeRTOS for PULP based systems (GitHub repository)

[8] EPI Power Managment Firmware