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SSR combined with FREP in LLVM/Clang (M/1-3S)

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Currently leveraging the Xssr and Xfrep extensions of Snitch require manual assembly programming. This includes programming the SSR address generators, enabling SSR semantics of a region of code, discouraging the compiler from using the stream registers for regular code, and inserting FREP as appropriate. We believe that for simple cases a lot of this work can be done directly by the compiler, such that leveraging SSR/FREP does not require manual assembly, but “only” adherence to a specific “loop coding style”. In a very crude prototype, we have explored how the RISC-V LLVM backend could be extended to automatically detect loads/stores that are amenable for SSR replacement, and to actually insert the necessary code. Expanding a transformation pass like this to cover also FREP and more complex loops would be the target of this thesis. Besides trying to do all the magic automatically, there would also be ample benefit in coming up with a scheme of compiler intrinsics that give the programmer control over which SSRs are used and how FREP is executed as a first step. This could include things like address generation configuration, “popping” a value from a stream, and marking a set of float operations as a dedicated FREP loop.

Further reading
Requirements
  • C/C++, Python programming skills
  • Compiler design know-how
  • Interest in code generation
  • Interest in or experience with the LLVM/Clang codebase
  • Ability to endure soul-crunching hardware simulation environments

Composition: 50% Implementation, 30% Arhitecture, 20% Evaluation

Project Supervisors

Co-supervised by Prof. Torsten Hoefler's group

  • Alexandru Calotoiu -- acalotoiu at inf.ethz.ch