Difference between revisions of "Shared Correlation Accelerator for an RF SoC"
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Revision as of 15:24, 24 November 2017
We are currently working on designing Radio Frequency (RF) Systems on a chip (SoCs) for the Internet of Things (IoT). Requirements for these devices often include data connectivity and location information. A drone may, for instance, use both GPS and cellular positioning to increase the accuracy of the location estimate. We want to integrate both functionalities on a single chip.
Positioning and network synchronization rely on performing a large number of cross-correlations in real-time. Due to the large throughput requirements, large accelerators are required. Instead of using a dedicated circuit for each standard, we would like to share a single, flexible accelerator for all these tasks.
The goal of this project is, to develop a shared correlation accelerator for our RF SoC. This unit should support both positioning, as well as the synchronization for NB-IoT and eMTC. To do this, you will study the algorithms to quickly calculate a large number of cross-correlations. Using this knowledge, you will develop the accelerator in VHDL, or using High-Level Synthesis (HLS). It should be able to meet the throughput requirements of 100M correlation results/s, while keeping the area as low as possible.
Once you have implemented and verified the unit, you may tape out your own chip, or test it in our FPGA testbed.
- VLSI I
- VLSI II/III (for an ASIC tapeout)
Status: In Progress
- Student: Sascha Giger
- Supervision: Stefan Lippuner
- 20% Theory, Algorithms and Simulation
- 50% Implementation (HLS/VHDL)
- 30% ASIC Implementation / FPGA Integration