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Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC

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Top: Simplified trellis as used in the SOVE algorithm. Bottom: Layout of the RazorEDGE physical layer baseband ASIC. The highlighted area is occupied by the SOVE block.




Stefan Zwicky






Evolved EDGE is supposed to reduce the capacity gap of GSM/EDGE cellular networks to 3G networks by increasing the spectral efficiency in various ways. The high throughput comes at the cost of increased receiver complexity and typical GSM/EDGE baseband architectures with a DSP might be no longer feasible. Thus, the aim of this project is the development of a complete baseband processing ASIC to demonstrate the advantages of a dedicated hardware solution.

The ASIC comprises a digital front-end, a detector block including interference cancellation and channel equalization, as well as a channel decoder block with hybrid ARQ management. Furthermore, the chip is capable of combining data from two antennas to exploit receive diversity.

One of the most challenging parts of the design is the channel equalizer and detector block which must be capable of handling modulation orders up to 32-QAM and intersymbol interference over 7 symbols. The soft-output Viterbi equalizer (SOVE) proved to be the optimal solution. The algorithm is similar to the well-known BCJR algorithm, but the backward iteration is omitted. Instead, the decision on a symbol is done with a certain delay. In the figure, the reliability information about the red/green symbol corresponding to stage k-2 is obtained by comparing the red/green branch metrics at stage k.