User contributions
From iis-projects
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- 11:49, 13 March 2024 (diff | hist) . . (-22) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (current)
- 11:49, 13 March 2024 (diff | hist) . . (+76) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Status: In progress)
- 11:47, 13 March 2024 (diff | hist) . . (+2) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (current)
- 11:45, 13 March 2024 (diff | hist) . . (-4) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (current)
- 11:44, 13 March 2024 (diff | hist) . . (+15) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Status: Available)
- 12:53, 7 March 2024 (diff | hist) . . (+7) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→References) (current)
- 12:52, 7 March 2024 (diff | hist) . . (+197) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 14:05, 5 March 2024 (diff | hist) . . (-109) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Status: Available)
- 17:40, 1 March 2024 (diff | hist) . . (+91) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Status: Available)
- 21:33, 22 February 2024 (diff | hist) . . (-18) . . User:Colluca (→Luca Colagrande) (current)
- 21:30, 22 February 2024 (diff | hist) . . (+14) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Detailed task description)
- 21:28, 22 February 2024 (diff | hist) . . (+7,539) . . N A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (Created page with "<!-- A RISC-V ISA Extension for Scalar Chaining in Snitch (1M) --> Category:Digital Category:High Performance SoCs Category:2024 Category:Master Thesis Cate...")
- 19:52, 22 February 2024 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (current)
- 19:51, 22 February 2024 (diff | hist) . . (+4) . . Efficient collective communications in FlooNoC (1M)
- 16:54, 21 February 2024 (diff | hist) . . (+81) . . Efficient collective communications in FlooNoC (1M) (→Status: Available)
- 16:35, 16 February 2024 (diff | hist) . . (-1) . . User:Colluca (→Luca Colagrande)
- 16:34, 16 February 2024 (diff | hist) . . (+34) . . User:Colluca (→Luca Colagrande)
- 12:43, 3 November 2023 (diff | hist) . . (0) . . User:Colluca (→Luca Colagrande)
- 12:42, 3 November 2023 (diff | hist) . . (+7) . . User:Colluca (→Luca Colagrande)
- 12:42, 3 November 2023 (diff | hist) . . (+51) . . User:Colluca (→Luca Colagrande)
- 12:28, 3 November 2023 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:28, 3 November 2023 (diff | hist) . . (+6) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:21, 3 November 2023 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:20, 3 November 2023 (diff | hist) . . (+108) . . N File:Floonoc paper fig4.png (Physical implementation of FlooNoC connecting a mesh of compute tiles in GlobalFoundries’ 12 nm technology) (current)
- 12:18, 3 November 2023 (diff | hist) . . (+59) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:17, 3 November 2023 (diff | hist) . . (-74) . . Efficient collective communications in FlooNoC (1M) (→Project description)
- 12:13, 3 November 2023 (diff | hist) . . (+12) . . Efficient collective communications in FlooNoC (1M) (→Project description)
- 12:12, 3 November 2023 (diff | hist) . . (+5,693) . . N Efficient collective communications in FlooNoC (1M) (Created page with "<!-- Efficient collective communications in FlooNoC (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis Category:H...")
- 11:21, 20 October 2023 (diff | hist) . . (+180) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:51, 17 October 2023 (diff | hist) . . (+138) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (current)
- 09:57, 17 October 2023 (diff | hist) . . (+107) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Stretch goals)
- 09:57, 17 October 2023 (diff | hist) . . (+73) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Detailed task description)
- 09:56, 17 October 2023 (diff | hist) . . (-67) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Stretch goals)
- 11:37, 16 October 2023 (diff | hist) . . (+131) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 15:12, 3 October 2023 (diff | hist) . . (-19) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:12, 3 October 2023 (diff | hist) . . (0) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:11, 3 October 2023 (diff | hist) . . (+7) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:11, 3 October 2023 (diff | hist) . . (+21) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:10, 3 October 2023 (diff | hist) . . (+272) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 18:22, 29 September 2023 (diff | hist) . . (+2) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 18:21, 29 September 2023 (diff | hist) . . (+2) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Status: Available)
- 18:21, 29 September 2023 (diff | hist) . . (+79) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 18:19, 29 September 2023 (diff | hist) . . (+2) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 18:19, 29 September 2023 (diff | hist) . . (+83) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 18:17, 29 September 2023 (diff | hist) . . (-2) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 18:16, 29 September 2023 (diff | hist) . . (+3) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Status: Reserved)
- 13:46, 5 September 2023 (diff | hist) . . (+91) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Status: Available)
- 11:20, 5 September 2023 (diff | hist) . . (+4) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 11:20, 5 September 2023 (diff | hist) . . (+62) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 17:18, 4 September 2023 (diff | hist) . . (-19) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
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