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- 18:03, 31 January 2021 (diff | hist) . . (-7) . . Manycore System on FPGA (M/S/G)
- 18:02, 31 January 2021 (diff | hist) . . (+4) . . Manycore System on FPGA (M/S/G) (→Project Description)
- 18:02, 31 January 2021 (diff | hist) . . (0) . . Manycore System on FPGA (M/S/G)
- 17:58, 31 January 2021 (diff | hist) . . (+1,686) . . Manycore System on FPGA (M/S/G)
- 17:18, 31 January 2021 (diff | hist) . . (0) . . N File:Mempool logo.pdf (current)
- 17:12, 31 January 2021 (diff | hist) . . (-1) . . Transforming MemPool into a CGRA (M)
- 17:12, 31 January 2021 (diff | hist) . . (-2) . . Transforming MemPool into a CGRA (M)
- 17:10, 31 January 2021 (diff | hist) . . (+4) . . Transforming MemPool into a CGRA (M) (→Introduction)
- 17:10, 31 January 2021 (diff | hist) . . (0) . . N File:Mempool cgra.png (current)
- 17:08, 31 January 2021 (diff | hist) . . (+13,058) . . N Transforming MemPool into a CGRA (M) (Created page with "<!-- Transforming MemPool into a CGRA (M) --> = Overview = == Status: Available == * Type: Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sriedel...")
- 00:46, 31 January 2021 (diff | hist) . . (+6,925) . . N Manycore System on FPGA (M/S/G) (Created page with "<!-- Manycore System on FPGA --> = Overview = == Status: Available == * Type: Bachelor/Semester/Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sri...")
- 19:19, 29 January 2021 (diff | hist) . . (-18) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (current)
- 19:16, 29 January 2021 (diff | hist) . . (-18) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 19:15, 29 January 2021 (diff | hist) . . (0) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 19:13, 29 January 2021 (diff | hist) . . (-1) . . ASIC Design Projects (→How does it work) (current)
- 19:12, 29 January 2021 (diff | hist) . . (+18) . . VLSI Implementation of a 5G Ciphering Accelerator
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . Event-Driven Convolutional Neural Network Modular Accelerator (→Links) (current)
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . Spiking Neural Network for Autonomous Navigation (→Links) (current)
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (→Links) (current)
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . Level Crossing ADC For a Many Channels Neural Recording Interface (→Links) (current)
- 19:08, 29 January 2021 (diff | hist) . . (+18) . . Resilient Brain-Inspired Hyperdimensional Computing Architectures (current)
- 19:06, 29 January 2021 (diff | hist) . . (+76) . . ASIC Design Projects (→Newly available ASIC design projects from our group)
- 19:05, 29 January 2021 (diff | hist) . . (+1) . . Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (current)
- 19:03, 29 January 2021 (diff | hist) . . (-108) . . ASIC Development of 5G-NR LDPC Decoder
- 14:28, 28 January 2021 (diff | hist) . . (+328) . . ASIC Design Projects
- 00:25, 28 January 2021 (diff | hist) . . (+33) . . Digital (→Topic List)
- 00:22, 28 January 2021 (diff | hist) . . (+18) . . Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- 00:21, 28 January 2021 (diff | hist) . . (+156) . . ASIC Design Projects
- 00:39, 24 January 2021 (diff | hist) . . (0) . . User:Sriedel (current)
- 19:07, 20 January 2021 (diff | hist) . . (-4) . . MemPool on HERO (1S) (current)
- 19:04, 20 January 2021 (diff | hist) . . (+12,430) . . N Efficient Synchronization of Manycore Systems (M/1S) (Created page with "<!-- Eliminating the polling of locks (M/1S) --> = Overview = == Status: Available == * Type: Semester/Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :U...")
- 12:07, 20 January 2021 (diff | hist) . . (+21) . . An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- 12:07, 20 January 2021 (diff | hist) . . (0) . . m Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- 19:21, 2 November 2020 (diff | hist) . . (0) . . MemPool on HERO (1S)
- 19:19, 2 November 2020 (diff | hist) . . (+1) . . ISA extensions in the Snitch Processor for Signal Processing (1M)
- 19:15, 2 November 2020 (diff | hist) . . (0) . . ISA extensions in the Snitch Processor for Signal Processing (1M)
- 19:08, 2 November 2020 (diff | hist) . . (-1) . . User:Sriedel
- 19:08, 2 November 2020 (diff | hist) . . (+1) . . User:Sriedel
- 19:07, 2 November 2020 (diff | hist) . . (-33) . . ISA extensions in the Snitch Processor for Signal Processing (1M)
- 19:06, 2 November 2020 (diff | hist) . . (0) . . MemPool on HERO (1S)
- 19:05, 2 November 2020 (diff | hist) . . (-9) . . ISA extensions in the Snitch Processor for Signal Processing (1M)
- 19:03, 2 November 2020 (diff | hist) . . (+9,304) . . N ISA extensions in the Snitch Processor for Signal Processing (1M) (Created page with "<!-- (M/1-3S/1-3B/2-3G): ISA extensions in the Snitch Processor for Signal Processing --> = Introduction = Striving for high image quality, even on mobile devices, has lead...")
- 18:43, 2 November 2020 (diff | hist) . . (+2) . . MemPool on HERO (1S)
- 18:42, 2 November 2020 (diff | hist) . . (-6,163) . . MemPool on HERO (Blanked the page) (current)
- 18:42, 2 November 2020 (diff | hist) . . (+6,163) . . N MemPool on HERO (1S) (Created page with "== Introduction == Heterogeneous systems combine a general-purpose host processor with domain-specific Programmable Many-Core Accelerators (PMCAs). Such systems are highly ve...")
- 18:02, 2 November 2020 (diff | hist) . . (+101) . . MemPool on HERO (→Status: In progress)
- 18:00, 2 November 2020 (diff | hist) . . (+6,062) . . N MemPool on HERO (Created page with "== Introduction == Heterogeneous systems combine a general-purpose host processor with domain-specific Programmable Many-Core Accelerators (PMCAs). Such systems are highly ve...")
- 17:41, 2 November 2020 (diff | hist) . . (+572) . . User:Sriedel
- 16:35, 2 December 2019 (diff | hist) . . (-5) . . User:Sriedel
- 16:33, 2 December 2019 (diff | hist) . . (+360) . . N User:Sriedel (Created page with "== Samuel Riedel == * '''e-mail''': [mailto:sriedel@iis.ee.ethz.ch sriedel@iis.ee.ethz.ch] Category:Digital ==Interests== * Computer and System Architecture * High Perfo...")
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