User contributions
From iis-projects
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- 18:47, 24 November 2023 (diff | hist) . . (-1) . . Taping a Safer Silicon Implementation of Snitch (M/2-3S) (current)
- 11:18, 3 November 2023 (diff | hist) . . (+2,414) . . N Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) (Created page with "<!-- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) --> Category:Digital Category:High Performance SoCs [...") (current)
- 10:53, 3 November 2023 (diff | hist) . . (-19) . . Taping a Safer Silicon Implementation of Snitch (M/2-3S) (→Status: Available)
- 10:52, 3 November 2023 (diff | hist) . . (+2,237) . . N Taping a Safer Silicon Implementation of Snitch (M/2-3S) (Created page with "<!-- Creating Taping a Safer Silicon Implementation of Snitch (M/2-3S) (1-3S/B/2-3G) --> Category:Digital Category:ASIC Category:High Performance SoCs Category:...")
- 10:27, 3 November 2023 (diff | hist) . . (+2,332) . . N Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) (Created page with "<!-- Creating Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C...") (current)
- 10:25, 3 November 2023 (diff | hist) . . (-2,461) . . Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (Blanked the page) (current)
- 10:24, 3 November 2023 (diff | hist) . . (+162) . . Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (→Project) (current)
- 10:21, 3 November 2023 (diff | hist) . . (0) . . Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- 10:21, 3 November 2023 (diff | hist) . . (0) . . Towards Formal Verification of the iDMA Engine (1-3S/B) (current)
- 10:21, 3 November 2023 (diff | hist) . . (+78) . . Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- 10:19, 3 November 2023 (diff | hist) . . (0) . . IP-Based SoC Generation and Configuration (1-3S/B) (current)
- 09:55, 3 November 2023 (diff | hist) . . (-1) . . Creating A Boundry Scan Generator (1-3S/B/2-3G) (current)
- 09:46, 3 November 2023 (diff | hist) . . (+137) . . Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (→Introduction)
- 09:45, 3 November 2023 (diff | hist) . . (+68) . . Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (→Project)
- 09:44, 3 November 2023 (diff | hist) . . (+81) . . Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (→Introduction)
- 09:39, 3 November 2023 (diff | hist) . . (0) . . Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) (current)
- 09:38, 3 November 2023 (diff | hist) . . (0) . . Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (current)
- 09:38, 3 November 2023 (diff | hist) . . (0) . . Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (current)
- 09:36, 3 November 2023 (diff | hist) . . (0) . . Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (current)
- 09:36, 3 November 2023 (diff | hist) . . (0) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (current)
- 09:36, 3 November 2023 (diff | hist) . . (0) . . Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (current)
- 09:35, 3 November 2023 (diff | hist) . . (0) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (current)
- 09:34, 3 November 2023 (diff | hist) . . (+5,474) . . N Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (Created page with "<!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --> Category:Digital Category:High Performance SoCs Category:Comp...")
- 09:34, 3 November 2023 (diff | hist) . . (-5,474) . . Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) (Blanked the page) (current)
- 09:30, 3 November 2023 (diff | hist) . . (+5,474) . . N Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) (Created page with "<!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --> Category:Digital Category:High Performance SoCs Category:Comp...")
- 09:30, 3 November 2023 (diff | hist) . . (-5,443) . . Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) (Blanked the page) (current)
- 09:28, 3 November 2023 (diff | hist) . . (0) . . Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (current)
- 09:28, 3 November 2023 (diff | hist) . . (0) . . Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (current)
- 09:27, 3 November 2023 (diff | hist) . . (0) . . Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (current)
- 09:27, 3 November 2023 (diff | hist) . . (0) . . Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (current)
- 09:25, 3 November 2023 (diff | hist) . . (+2) . . Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- 09:24, 3 November 2023 (diff | hist) . . (-1) . . High Performance SoCs (→Who are we)
- 11:35, 29 August 2023 (diff | hist) . . (+1,489) . . N Creating A Boundry Scan Generator (1-3S/B/2-3G) (Created page with "<!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) --> Category:Digital Category:ASIC Category:High Performance SoCs Category:Computer Architecture Catego...")
- 11:29, 29 August 2023 (diff | hist) . . (+5) . . Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- 11:26, 29 August 2023 (diff | hist) . . (-17) . . Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
- 11:24, 29 August 2023 (diff | hist) . . (0) . . N Category:2023 (Created blank page) (current)
- 11:24, 29 August 2023 (diff | hist) . . (+18) . . Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- 10:35, 29 August 2023 (diff | hist) . . (+2,192) . . N Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (Created page with "<!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer...")
- 10:15, 29 August 2023 (diff | hist) . . (-7) . . Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (→References)
- 10:14, 29 August 2023 (diff | hist) . . (-190) . . Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- 10:14, 29 August 2023 (diff | hist) . . (+2,934) . . N Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:FPGA Category:2023 Category:Master Thesis Category:Tbenz ...")
- 09:46, 29 August 2023 (diff | hist) . . (+1,620) . . N Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (Created page with "<!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C...")
- 09:31, 29 August 2023 (diff | hist) . . (+1) . . Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (current)
- 09:31, 29 August 2023 (diff | hist) . . (+1) . . A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- 09:31, 29 August 2023 (diff | hist) . . (-2) . . Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- 09:49, 5 January 2023 (diff | hist) . . (-1) . . m A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- 09:48, 5 January 2023 (diff | hist) . . (-1) . . m Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- 08:07, 8 November 2022 (diff | hist) . . (+2,089) . . N Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (Created page with "<!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture [...")
- 07:52, 8 November 2022 (diff | hist) . . (0) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- 07:51, 8 November 2022 (diff | hist) . . (-9) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
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