User contributions
From iis-projects
- 11:35, 29 August 2023 (diff | hist) . . (+1,489) . . N Creating A Boundry Scan Generator (1-3S/B/2-3G) (Created page with "<!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) --> Category:Digital Category:ASIC Category:High Performance SoCs Category:Computer Architecture Catego...") (current)
- 11:29, 29 August 2023 (diff | hist) . . (+5) . . Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (current)
- 11:26, 29 August 2023 (diff | hist) . . (-17) . . Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (current)
- 11:24, 29 August 2023 (diff | hist) . . (0) . . N Category:2023 (Created blank page) (current)
- 11:24, 29 August 2023 (diff | hist) . . (+18) . . Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- 10:35, 29 August 2023 (diff | hist) . . (+2,192) . . N Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (Created page with "<!-- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer...")
- 10:15, 29 August 2023 (diff | hist) . . (-7) . . Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (→References) (current)
- 10:14, 29 August 2023 (diff | hist) . . (-190) . . Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- 10:14, 29 August 2023 (diff | hist) . . (+2,934) . . N Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:FPGA Category:2023 Category:Master Thesis Category:Tbenz ...")
- 09:46, 29 August 2023 (diff | hist) . . (+1,620) . . N Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (Created page with "<!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C...")
- 09:31, 29 August 2023 (diff | hist) . . (+1) . . Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (current)
- 09:31, 29 August 2023 (diff | hist) . . (+1) . . A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (current)
- 09:31, 29 August 2023 (diff | hist) . . (-2) . . Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (current)
- 09:49, 5 January 2023 (diff | hist) . . (-1) . . m A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- 09:48, 5 January 2023 (diff | hist) . . (-1) . . m Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- 08:07, 8 November 2022 (diff | hist) . . (+2,089) . . N Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (Created page with "<!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture [...") (current)
- 07:52, 8 November 2022 (diff | hist) . . (0) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (current)
- 07:51, 8 November 2022 (diff | hist) . . (-9) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- 07:46, 8 November 2022 (diff | hist) . . (+1,417) . . N Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (Created page with "<!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architect...")
- 12:55, 7 November 2022 (diff | hist) . . (+1,794) . . N Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (Created page with "<!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture...") (current)
- 11:56, 7 November 2022 (diff | hist) . . (+1,776) . . N Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (Created page with "<!-- Creating Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:...")
- 11:44, 7 November 2022 (diff | hist) . . (+1,705) . . N Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (Created page with "<!-- Creating Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) --> Category:Di...") (current)
- 11:27, 7 November 2022 (diff | hist) . . (-8) . . Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (current)
- 11:25, 7 November 2022 (diff | hist) . . (+2,184) . . N Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (Created page with "<!-- Creating Towards a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:...")
- 10:52, 7 November 2022 (diff | hist) . . (+3) . . Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- 10:51, 7 November 2022 (diff | hist) . . (+3) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 10:51, 7 November 2022 (diff | hist) . . (0) . . Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- 10:51, 7 November 2022 (diff | hist) . . (+2) . . Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- 18:20, 15 August 2022 (diff | hist) . . (+2,710) . . N Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (Created page with "<!-- Creating Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Arch...") (current)
- 21:08, 2 August 2022 (diff | hist) . . (+119) . . User:Tbenz (current)
- 21:07, 2 August 2022 (diff | hist) . . (+29) . . Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (current)
- 21:07, 2 August 2022 (diff | hist) . . (+29) . . Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- 21:07, 2 August 2022 (diff | hist) . . (+140) . . Towards Formal Verification of the iDMA Engine (1-3S/B) (current)
- 21:06, 2 August 2022 (diff | hist) . . (+1,026) . . User:Jungvi
- 21:04, 2 August 2022 (diff | hist) . . (0) . . N User:Jungvi (Created blank page)
- 21:04, 2 August 2022 (diff | hist) . . (+1,568) . . N Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (Created page with "<!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture...")
- 20:53, 2 August 2022 (diff | hist) . . (+1,814) . . N Towards Formal Verification of the iDMA Engine (1-3S/B) (Created page with "<!-- Creating Towards Formal Verification of the iDMA Engine (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Categor...")
- 10:16, 13 July 2022 (diff | hist) . . (+1,378) . . N Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) (Created page with "<!-- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture...") (current)
- 08:51, 12 July 2022 (diff | hist) . . (-3) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 08:50, 12 July 2022 (diff | hist) . . (-1) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 08:50, 12 July 2022 (diff | hist) . . (-1) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 10:20, 27 June 2022 (diff | hist) . . (-2) . . Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (→Introduction)
- 10:20, 27 June 2022 (diff | hist) . . (-1) . . m Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (→Introduction)
- 10:19, 27 June 2022 (diff | hist) . . (+1,621) . . N Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (Created page with "<!-- Creating Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:...")
- 12:56, 21 June 2022 (diff | hist) . . (+1) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 12:55, 21 June 2022 (diff | hist) . . (-1) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 12:53, 21 June 2022 (diff | hist) . . (+1,928) . . N Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (Created page with "<!-- Creating Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) --> Category:Digital Category:High Performance SoCs Category:Computer Ar...")
- 12:27, 21 June 2022 (diff | hist) . . (+2,189) . . N Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (Created page with "<!-- Creating Extension and Evaluation of TinyDMA (1-2S/B/2-3G) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2022...")
- 12:13, 21 June 2022 (diff | hist) . . (-2) . . Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (current)
- 12:12, 21 June 2022 (diff | hist) . . (-2) . . Adding Linux Support to our DMA Engine (1-2S/B) (current)
- 11:50, 15 February 2022 (diff | hist) . . (+3) . . Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- 11:50, 15 February 2022 (diff | hist) . . (+3) . . m Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- 11:49, 15 February 2022 (diff | hist) . . (0) . . m Adding Linux Support to our DMA Engine (1-2S/B)
- 11:47, 15 February 2022 (diff | hist) . . (+3) . . m Adding Linux Support to our DMA Engine (1-2S/B)
- 18:11, 6 January 2022 (diff | hist) . . (+147) . . Fault Tolerance
- 17:35, 6 January 2022 (diff | hist) . . (0) . . N Category:2022 (Created blank page) (current)
- 17:34, 6 January 2022 (diff | hist) . . (0) . . Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- 17:30, 6 January 2022 (diff | hist) . . (+2,828) . . N Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (Created page with "<!-- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Ca...")
- 11:23, 3 January 2022 (diff | hist) . . (-1) . . Adding Linux Support to our DMA Engine (1-2S/B)
- 17:27, 19 November 2021 (diff | hist) . . (-1,734) . . Adding Linux Support to our DMA engine (1-2S/B) (Redirected page to Adding Linux Support to our DMA Engine (1-2S/B)) (current)
- 17:26, 19 November 2021 (diff | hist) . . (+1,795) . . N Adding Linux Support to our DMA Engine (1-2S/B) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2021 Category:Semester Thesis Category:Bachelor Thesis Catego...")
- 17:24, 19 November 2021 (diff | hist) . . (-3) . . Adding Linux Support to our DMA engine (1-2S/B)
- 17:23, 19 November 2021 (diff | hist) . . (+1,273) . . Adding Linux Support to our DMA engine (1-2S/B)
- 17:20, 19 November 2021 (diff | hist) . . (+525) . . N Adding Linux Support to our DMA engine (1-2S/B) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2021 Category:Semester Thesis Category:Bachelor Thesis Catego...")
- 17:10, 19 November 2021 (diff | hist) . . (+4,347) . . N Counter-based Fast Power Estimation using FPGAs (M/1-3S) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2021 Category:Semester Thesis Category:Master Thesis Category...")
- 16:48, 19 November 2021 (diff | hist) . . (0) . . High Performance SoCs (→Who are we)
- 13:35, 15 November 2021 (diff | hist) . . (0) . . User:Smazzola
- 13:34, 15 November 2021 (diff | hist) . . (+392) . . N User:Smazzola (Created page with "== Sergio Mazzola == ==Available Projects== <DynamicPageList> supresserrors = true category = Available category = Matheusd </DynamicPageList> ==Projects In Progress== <Dyna...")
- 13:33, 15 November 2021 (diff | hist) . . (0) . . N File:Smazzola face 1to1.png (current)
- 13:31, 15 November 2021 (diff | hist) . . (+260) . . High Performance SoCs (→Who are we)
- 13:15, 15 November 2021 (diff | hist) . . (+49) . . RISC-V base ISA for ultra-low-area cores (2-3G) (current)
- 20:11, 15 February 2021 (diff | hist) . . (-4) . . LLVM and DaCe for Snitch (1-2S) (→Status: In progress)
- 20:10, 15 February 2021 (diff | hist) . . (-1) . . LLVM and DaCe for Snitch (1-2S) (→Status: In progress)
- 20:09, 15 February 2021 (diff | hist) . . (0) . . N User:Alexandru.calotoiu (Created blank page) (current)
- 20:08, 15 February 2021 (diff | hist) . . (+37) . . Software-Defined Paging in the Snitch Cluster (2-3S) (current)
- 20:06, 15 February 2021 (diff | hist) . . (+62) . . SSR combined with FREP in LLVM/Clang (M/1-3S) (Redirected page to LLVM and DaCe for Snitch (1-2S)) (current)
- 20:05, 15 February 2021 (diff | hist) . . (+62) . . DaCe on Snitch (M/1-3S) (Redirected page to LLVM and DaCe for Snitch (1-2S)) (current)
- 20:03, 15 February 2021 (diff | hist) . . (+58) . . Snitch meets iCE40 (1-2S/B) (Redirected page to A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)) (current)
- 20:01, 15 February 2021 (diff | hist) . . (+7) . . Snitch meets iCE40 (1-2S/B)
- 20:00, 15 February 2021 (diff | hist) . . (+3) . . Quest for the smallest Turing-complete core (2-3G)
- 20:00, 15 February 2021 (diff | hist) . . (+1) . . Quest for the smallest Turing-complete core (2-3G)
- 20:00, 15 February 2021 (diff | hist) . . (+3) . . Quest for the smallest Turing-complete core (2-3G)
- 19:59, 15 February 2021 (diff | hist) . . (+39) . . N Outdated pitches (Redirected page to Category:Outdated pitches) (current)
- 19:54, 15 February 2021 (diff | hist) . . (+8) . . Quest for the smallest Turing-complete core (2-3G)
- 19:52, 15 February 2021 (diff | hist) . . (0) . . N Category:Outdated pitches (Created blank page) (current)
- 19:51, 15 February 2021 (diff | hist) . . (+8) . . Snitch meets iCE40 (1-2S/B)
- 19:47, 15 February 2021 (diff | hist) . . (+124) . . A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- 19:45, 15 February 2021 (diff | hist) . . (+8,260) . . N A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (create)
- 14:27, 18 January 2021 (diff | hist) . . (+2) . . An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (→Status: Available)
- 15:59, 12 January 2021 (diff | hist) . . (-1) . . Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- 19:00, 18 December 2020 (diff | hist) . . (0) . . N File:Rpc dram.png (current)
- 18:57, 18 December 2020 (diff | hist) . . (0) . . N Category:2021 (Created blank page) (current)
- 18:57, 18 December 2020 (diff | hist) . . (+29) . . N Category:Aottaviano (Redirected page to User:Aottaviano) (current)
- 18:56, 18 December 2020 (diff | hist) . . (+125) . . An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- 18:54, 18 December 2020 (diff | hist) . . (+398) . . N User:Aottaviano (Created page with "=Alessandro Ottaviano= ==Projects== ===Available Projects=== <DynamicPageList> category = Available category = Aottaviano suppresserrors=true </DynamicPageList> ===Projects...")
- 18:53, 18 December 2020 (diff | hist) . . (+8,115) . . N An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (create)
- 23:01, 4 December 2020 (diff | hist) . . (-1) . . Snitch meets iCE40 (1-2S/B)
- 17:36, 24 November 2020 (diff | hist) . . (0) . . N Category:Reserved (Created blank page) (current)
- 19:13, 19 November 2020 (diff | hist) . . (0) . . DaCe on Snitch (M/1-3S)
- 20:08, 11 November 2020 (diff | hist) . . (+90) . . Quest for the smallest Turing-complete core (2-3G)
- 20:07, 11 November 2020 (diff | hist) . . (+20) . . Quest for the smallest Turing-complete core (2-3G)
- 17:50, 11 November 2020 (diff | hist) . . (+174) . . SSR combined with FREP in LLVM/Clang (M/1-3S) (→Project Supervisors)
- 17:21, 11 November 2020 (diff | hist) . . (-1) . . SSR combined with FREP in LLVM/Clang (M/1-3S)
- 17:21, 11 November 2020 (diff | hist) . . (+190) . . High Performance SoCs
- 16:17, 11 November 2020 (diff | hist) . . (+131) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- 16:13, 11 November 2020 (diff | hist) . . (0) . . N File:Ibm blue gene q 2011.jpg (current)
- 15:25, 11 November 2020 (diff | hist) . . (+2,396) . . N Snitch meets iCE40 (1-2S/B) (Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Bachelor Thesis Category:Semester Thesis Category:Paulsc Category:Tbenz Ca...")
- 15:15, 11 November 2020 (diff | hist) . . (+390) . . Category:Bachelor Thesis (current)
- 15:13, 11 November 2020 (diff | hist) . . (0) . . N Category:Bachelor Thesis (Created blank page)
- 15:13, 11 November 2020 (diff | hist) . . (+29) . . IP-Based SoC Generation and Configuration (1-3S/B)
- 14:34, 11 November 2020 (diff | hist) . . (-20) . . Quest for the smallest Turing-complete core (2-3G)
- 14:34, 11 November 2020 (diff | hist) . . (+1,542) . . N Quest for the smallest Turing-complete core (2-3G) (Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Group Project Category:Paulsc Category:Tbenz Category:Available == Introduc...")
- 12:48, 11 November 2020 (diff | hist) . . (+384) . . Category:Group Project (current)
- 12:31, 11 November 2020 (diff | hist) . . (+2,227) . . N RISC-V base ISA for ultra-low-area cores (2-3G) (Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Group Project Category:Paulsc Category:Tbenz Category:Available == Introduc...")
- 21:47, 10 November 2020 (diff | hist) . . (+66) . . (M/1-2S): A Snitch-based Compute Accelerator for HERO (Redirected page to A Snitch-based Compute Accelerator for HERO (M/1-2S)) (current)
- 20:24, 10 November 2020 (diff | hist) . . (+3,764) . . N IP-Based SoC Generation and Configuration (1-3S/B) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Semester Thesis Category:Paulsc [[Category:Tbenz]...")
- 20:24, 10 November 2020 (diff | hist) . . (-3,764) . . IP-Based SoC Generation and Configuration (1-3S) (Blanked the page) (current)
- 19:35, 2 November 2020 (diff | hist) . . (-17) . . IP-Based SoC Generation and Configuration (1-3S)
- 19:35, 2 November 2020 (diff | hist) . . (-17) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 19:35, 2 November 2020 (diff | hist) . . (+17) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 19:34, 2 November 2020 (diff | hist) . . (+17) . . Software-Defined Paging in the Snitch Cluster (2-3S)
- 19:34, 2 November 2020 (diff | hist) . . (+17) . . IP-Based SoC Generation and Configuration (1-3S)
- 19:34, 2 November 2020 (diff | hist) . . (+17) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- 19:33, 2 November 2020 (diff | hist) . . (0) . . Heterogeneous Acceleration Systems (current)
- 19:31, 2 November 2020 (diff | hist) . . (+8,960) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:30, 2 November 2020 (diff | hist) . . (-25) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:29, 2 November 2020 (diff | hist) . . (-48) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:28, 2 November 2020 (diff | hist) . . (-8,886) . . ISA extensions in the Snitch Processor for Signal Processing (M) (Replaced content with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:Heterogeneous Acceleration Systems Category:Sriedel Category:...")
- 19:26, 2 November 2020 (diff | hist) . . (0) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:25, 2 November 2020 (diff | hist) . . (+1) . . High Performance SoCs (→Projects In Progress)
- 19:25, 2 November 2020 (diff | hist) . . (-17) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:24, 2 November 2020 (diff | hist) . . (-9,171) . . ISA extensions in the Snitch Processor for Signal Processing (1M) (Blanked the page) (current)
- 19:24, 2 November 2020 (diff | hist) . . (+9,171) . . N ISA extensions in the Snitch Processor for Signal Processing (M) (Created page with "= Introduction = Striving for high image quality, even on mobile devices, has lead to an increase in pixel count in smartphone cameras over the last decade [<nowiki/>#ref-...")
- 19:22, 2 November 2020 (diff | hist) . . (-92) . . ISA extensions in the Snitch Processor for Signal Processing (1M)
- 18:53, 2 November 2020 (diff | hist) . . (-2) . . MemPool on HERO (1S)
- 18:48, 2 November 2020 (diff | hist) . . (+28) . . N Category:Mperotti (Redirected page to Matteo Perotti) (current)
- 18:45, 2 November 2020 (diff | hist) . . (+28) . . User:Mperotti (Redirected page to Matteo Perotti) (current)
- 18:45, 2 November 2020 (diff | hist) . . (+25) . . N Matteo Perotti (Created page with "He is a dude doing stuff.")
- 18:34, 2 November 2020 (diff | hist) . . (+19) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:33, 2 November 2020 (diff | hist) . . (+74) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:24, 2 November 2020 (diff | hist) . . (-5) . . Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (→HDL Guidelines)
- 18:13, 2 November 2020 (diff | hist) . . (0) . . N Category:Group Project (Created blank page)
- 18:12, 2 November 2020 (diff | hist) . . (+26) . . N Category:Sriedel (Redirected page to User:Sriedel) (current)
- 18:10, 2 November 2020 (diff | hist) . . (+484) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:07, 2 November 2020 (diff | hist) . . (+147) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:05, 2 November 2020 (diff | hist) . . (+6) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:05, 2 November 2020 (diff | hist) . . (+406) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:01, 2 November 2020 (diff | hist) . . (0) . . N User:Mperotti (Created blank page)
- 18:01, 2 November 2020 (diff | hist) . . (+263) . . High Performance SoCs (→Who are we)
- 17:59, 2 November 2020 (diff | hist) . . (+1,334) . . N SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (Created page with "Coding conventions are an '''essential part''' of every large hardware (and software) project. They guide various '''non-functional aspects''' of the project and the source co...")
- 17:32, 2 November 2020 (diff | hist) . . (+1) . . Category:Smach (Redirected page to Stefan Mach) (current)
- 17:32, 2 November 2020 (diff | hist) . . (+24) . . N Category:Smach (Redirected page to User:Smach)
- 17:29, 2 November 2020 (diff | hist) . . (0) . . N Category:2020 (Created blank page) (current)
- 17:29, 2 November 2020 (diff | hist) . . (+1) . . Category:Fschuiki (Redirected page to Fabian Schuiki) (current)
- 17:28, 2 November 2020 (diff | hist) . . (+27) . . N Category:Fschuiki (Redirected page to User:Fschuiki)
- 17:28, 2 November 2020 (diff | hist) . . (+26) . . N Category:Zarubaf (Redirected page to User:Zarubaf) (current)
- 17:28, 2 November 2020 (diff | hist) . . (+25) . . N Category:Paulsc (Redirected page to User:Paulsc)
- 17:27, 2 November 2020 (diff | hist) . . (+5) . . User:Tbenz (→Thomas Benz)
- 17:26, 2 November 2020 (diff | hist) . . (+16) . . User:Tbenz (→Thomas Benz)
- 17:26, 2 November 2020 (diff | hist) . . (+24) . . N Category:Tbenz (Redirected page to User:Tbenz) (current)
- 13:52, 2 November 2020 (diff | hist) . . (-1) . . High Performance SoCs (→Who are we)
- 13:51, 2 November 2020 (diff | hist) . . (0) . . N File:Sriedel face pulp team.jpg (current)
- 13:50, 2 November 2020 (diff | hist) . . (+541) . . High Performance SoCs (→Who are we)
- 13:45, 2 November 2020 (diff | hist) . . (0) . . N File:Fschuiki face pulp team.jpg (current)
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- 13:07, 2 November 2020 (diff | hist) . . (-36) . . High Performance SoCs (→Completed Projects)
- 13:06, 2 November 2020 (diff | hist) . . (+36) . . High Performance SoCs (→Completed Projects)
- 13:05, 2 November 2020 (diff | hist) . . (+36) . . High Performance SoCs (→Projects In Progress)
- 13:05, 2 November 2020 (diff | hist) . . (+36) . . High Performance SoCs (→Available Projects)
- 13:03, 2 November 2020 (diff | hist) . . (-2,444) . . DaCe on Snitch (Blanked the page) (current)
- 13:03, 2 November 2020 (diff | hist) . . (+2,444) . . N DaCe on Snitch (M/1-3S) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Master Thesis Category:Semester Thesis Category...")
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- 13:02, 2 November 2020 (diff | hist) . . (+2,434) . . N SSR combined with FREP in LLVM/Clang (M/1-3S) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Master Thesis Category:Semester Thesis Category...")
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- 12:56, 2 November 2020 (diff | hist) . . (-8) . . Coherence-Capable Write-Back L1 Data Cache for Ariane (Redirected page to Coherence-Capable Write-Back L1 Data Cache for Ariane (M)) (current)
- 12:55, 2 November 2020 (diff | hist) . . (+2,789) . . N Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Master Thesis Category:Semester Thesis Category...")
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- 12:48, 2 November 2020 (diff | hist) . . (+5,092) . . N Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (Created page with "== Introduction == Heterogeneous systems combine a general-purpose host processor with domain-specific Programmable Many-Core Accelerators (PMCAs). Such systems are highly ve...")
- 12:48, 2 November 2020 (diff | hist) . . (-5,092) . . Implementation of a Heterogeneous System for Image Processing on an FPGA (Blanked the page) (current)
- 12:18, 2 November 2020 (diff | hist) . . (+11,105) . . N A Snitch-based Compute Accelerator for HERO (M/1-2S) (Created page with "<!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> = Overview = == Status: In progress == * Type: Semester Thesis * Semester: Autumn Semester 2020 * Student: No...")
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- 11:15, 2 November 2020 (diff | hist) . . (-2,660) . . IBM A2O Core (Blanked the page) (current)
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- 18:54, 30 October 2020 (diff | hist) . . (+35) . . IBM A2O Core
- 18:51, 30 October 2020 (diff | hist) . . (+189) . . IBM A2O Core
- 18:49, 30 October 2020 (diff | hist) . . (+2,437) . . N IBM A2O Core (Created page with "=Investigation of the high-performance multi-threaded OoO IBM A2O Core= IBM recently contributed their A2O processor core to the open-source community. The A2O is a 2-way mul...")
- 16:39, 26 October 2020 (diff | hist) . . (+525) . . High Performance SoCs (→Who are we)
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- 13:50, 22 October 2020 (diff | hist) . . (+452) . . User:Tbenz (→Thomas Benz)
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- 10:17, 22 October 2020 (diff | hist) . . (+180) . . User:Tbenz (→Projects)
- 10:45, 7 August 2020 (diff | hist) . . (+1) . . (M/1-2S): A Snitch-based Compute Accelerator for HERO
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- 09:25, 30 July 2020 (diff | hist) . . (+334) . . m (M/1-2S): A Snitch-based Compute Accelerator for HERO (Update by bot)
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- 09:25, 30 July 2020 (diff | hist) . . (0) . . File:Snitch-bd.png (Tbenz uploaded a new version of File:Snitch-bd.png)
