User contributions
From iis-projects
(newest | oldest) View (newer 50 | older 50) (20 | 50 | 100 | 250 | 500)
- 18:57, 18 December 2020 (diff | hist) . . (0) . . N Category:2021 (Created blank page) (current)
- 18:57, 18 December 2020 (diff | hist) . . (+29) . . N Category:Aottaviano (Redirected page to User:Aottaviano) (current)
- 18:56, 18 December 2020 (diff | hist) . . (+125) . . An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- 18:54, 18 December 2020 (diff | hist) . . (+398) . . N User:Aottaviano (Created page with "=Alessandro Ottaviano= ==Projects== ===Available Projects=== <DynamicPageList> category = Available category = Aottaviano suppresserrors=true </DynamicPageList> ===Projects...")
- 18:53, 18 December 2020 (diff | hist) . . (+8,115) . . N An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (create)
- 23:01, 4 December 2020 (diff | hist) . . (-1) . . Snitch meets iCE40 (1-2S/B)
- 17:36, 24 November 2020 (diff | hist) . . (0) . . N Category:Reserved (Created blank page) (current)
- 19:13, 19 November 2020 (diff | hist) . . (0) . . DaCe on Snitch (M/1-3S)
- 20:08, 11 November 2020 (diff | hist) . . (+90) . . Quest for the smallest Turing-complete core (2-3G)
- 20:07, 11 November 2020 (diff | hist) . . (+20) . . Quest for the smallest Turing-complete core (2-3G)
- 17:50, 11 November 2020 (diff | hist) . . (+174) . . SSR combined with FREP in LLVM/Clang (M/1-3S) (→Project Supervisors)
- 17:21, 11 November 2020 (diff | hist) . . (-1) . . SSR combined with FREP in LLVM/Clang (M/1-3S)
- 17:21, 11 November 2020 (diff | hist) . . (+190) . . High Performance SoCs
- 16:17, 11 November 2020 (diff | hist) . . (+131) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- 16:13, 11 November 2020 (diff | hist) . . (0) . . N File:Ibm blue gene q 2011.jpg (current)
- 15:25, 11 November 2020 (diff | hist) . . (+2,396) . . N Snitch meets iCE40 (1-2S/B) (Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Bachelor Thesis Category:Semester Thesis Category:Paulsc Category:Tbenz Ca...")
- 15:15, 11 November 2020 (diff | hist) . . (+390) . . Category:Bachelor Thesis (current)
- 15:13, 11 November 2020 (diff | hist) . . (0) . . N Category:Bachelor Thesis (Created blank page)
- 15:13, 11 November 2020 (diff | hist) . . (+29) . . IP-Based SoC Generation and Configuration (1-3S/B)
- 14:34, 11 November 2020 (diff | hist) . . (-20) . . Quest for the smallest Turing-complete core (2-3G)
- 14:34, 11 November 2020 (diff | hist) . . (+1,542) . . N Quest for the smallest Turing-complete core (2-3G) (Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Group Project Category:Paulsc Category:Tbenz Category:Available == Introduc...")
- 12:48, 11 November 2020 (diff | hist) . . (+384) . . Category:Group Project (current)
- 12:31, 11 November 2020 (diff | hist) . . (+2,227) . . N RISC-V base ISA for ultra-low-area cores (2-3G) (Created page with "Category:Digital Category:High Performance SoCs Category:2020 Category:Group Project Category:Paulsc Category:Tbenz Category:Available == Introduc...")
- 21:47, 10 November 2020 (diff | hist) . . (+66) . . (M/1-2S): A Snitch-based Compute Accelerator for HERO (Redirected page to A Snitch-based Compute Accelerator for HERO (M/1-2S)) (current)
- 20:24, 10 November 2020 (diff | hist) . . (+3,764) . . N IP-Based SoC Generation and Configuration (1-3S/B) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Semester Thesis Category:Paulsc [[Category:Tbenz]...")
- 20:24, 10 November 2020 (diff | hist) . . (-3,764) . . IP-Based SoC Generation and Configuration (1-3S) (Blanked the page) (current)
- 19:35, 2 November 2020 (diff | hist) . . (-17) . . IP-Based SoC Generation and Configuration (1-3S)
- 19:35, 2 November 2020 (diff | hist) . . (-17) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 19:35, 2 November 2020 (diff | hist) . . (+17) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 19:34, 2 November 2020 (diff | hist) . . (+17) . . Software-Defined Paging in the Snitch Cluster (2-3S)
- 19:34, 2 November 2020 (diff | hist) . . (+17) . . IP-Based SoC Generation and Configuration (1-3S)
- 19:34, 2 November 2020 (diff | hist) . . (+17) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- 19:33, 2 November 2020 (diff | hist) . . (0) . . Heterogeneous Acceleration Systems (current)
- 19:31, 2 November 2020 (diff | hist) . . (+8,960) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:30, 2 November 2020 (diff | hist) . . (-25) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:29, 2 November 2020 (diff | hist) . . (-48) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:28, 2 November 2020 (diff | hist) . . (-8,886) . . ISA extensions in the Snitch Processor for Signal Processing (M) (Replaced content with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:Heterogeneous Acceleration Systems Category:Sriedel Category:...")
- 19:26, 2 November 2020 (diff | hist) . . (0) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:25, 2 November 2020 (diff | hist) . . (+1) . . High Performance SoCs (→Projects In Progress)
- 19:25, 2 November 2020 (diff | hist) . . (-17) . . ISA extensions in the Snitch Processor for Signal Processing (M)
- 19:24, 2 November 2020 (diff | hist) . . (-9,171) . . ISA extensions in the Snitch Processor for Signal Processing (1M) (Blanked the page) (current)
- 19:24, 2 November 2020 (diff | hist) . . (+9,171) . . N ISA extensions in the Snitch Processor for Signal Processing (M) (Created page with "= Introduction = Striving for high image quality, even on mobile devices, has lead to an increase in pixel count in smartphone cameras over the last decade [<nowiki/>#ref-...")
- 19:22, 2 November 2020 (diff | hist) . . (-92) . . ISA extensions in the Snitch Processor for Signal Processing (1M)
- 18:53, 2 November 2020 (diff | hist) . . (-2) . . MemPool on HERO (1S)
- 18:48, 2 November 2020 (diff | hist) . . (+28) . . N Category:Mperotti (Redirected page to Matteo Perotti) (current)
- 18:45, 2 November 2020 (diff | hist) . . (+28) . . User:Mperotti (Redirected page to Matteo Perotti) (current)
- 18:45, 2 November 2020 (diff | hist) . . (+25) . . N Matteo Perotti (Created page with "He is a dude doing stuff.")
- 18:34, 2 November 2020 (diff | hist) . . (+19) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:33, 2 November 2020 (diff | hist) . . (+74) . . SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- 18:24, 2 November 2020 (diff | hist) . . (-5) . . Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (→HDL Guidelines)
(newest | oldest) View (newer 50 | older 50) (20 | 50 | 100 | 250 | 500)