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Showing below up to 50 results in range #1 to #50.
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- High Performance Cellular Receivers in Very Advanced CMOS (2 revisions)
- Implementation of a 2-D model for Li-ion batteries (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (2 revisions)
- Smart Patch For Heath Care And Rehabilitation (2 revisions)
- A Post-Simulation Trace-Based RISC-V GDB Debugging Server (2 revisions)
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings (2 revisions)
- Accelerators for object detection and tracking (2 revisions)
- Test project (2 revisions)
- Triple-Core PULPissimo (2 revisions)
- Deep Unfolding of Iterative Optimization Algorithms (2 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (2 revisions)
- An Efficient Compiler Backend for Snitch (1S/B) (2 revisions)
- Successive Interference Cancellation for 3G Downlink (2 revisions)
- Optimal System Duty Cycling (2 revisions)
- Accurate deep learning inference using computational memory (2 revisions)
- Quantum Transport Modeling of Interband Cascade Lasers (ICL) (2 revisions)
- Autonomous Smart Sensors for IoT (2 revisions - redirect page)
- BirdGuard (2 revisions)
- Mixed Signal IC Design (2 revisions)
- System on Chips for IoTs (2 revisions - redirect page)
- Data Mapping for Unreliable Memories (2 revisions)
- High-Resolution, Calibrated Folding ADCs (2 revisions)
- PREM Intervals and Loop Tiling (2 revisions)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (2 revisions)
- AXI-based Network on Chip (NoC) system (2 revisions)
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) (2 revisions)
- Audio Visual Speech Recognition (1S/1M) (2 revisions)
- Kinetic Energy Harvesting For Autonomous Smart Watches (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) (2 revisions)
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA (2 revisions)
- Low Precision Ara for ML (2 revisions)
- Christoph Leitner (2 revisions)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (2 revisions - redirect page)
- RazorEDGE (2 revisions - redirect page)
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon (2 revisions)
- Towards Flexible and Printable Wearables (2 revisions)
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks (2 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (2 revisions)
- Ab-initio Simulation of Strained Thermoelectric Materials (2 revisions)
- Wake Up Radio For Energy Efficient Communication System and IC Design (2 revisions)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (2 revisions)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (2 revisions)
- Network-off-Chip (M) (2 revisions)
- Design of low mismatch DAC used for VAD (2 revisions)
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Piezoelectrics (1 S/B) (2 revisions - redirect page)
- Research (2 revisions)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M) (2 revisions)
- Short Range Radars For Biomedical Application (2 revisions)
- Low Resolution Neural Networks (2 revisions)
- Norbert Felber (2 revisions)