Pages with the fewest revisions

Showing below up to 50 results in range #1 to #50.

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1. XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory‏‎ (2 revisions)
2. Project Meetings‏‎ (2 revisions)
3. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))‏‎ (2 revisions)
4. Cryptography‏‎ (2 revisions)
5. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks‏‎ (2 revisions)
6. Norbert Felber‏‎ (2 revisions)
7. Prasadar‏‎ (2 revisions)
8. VLSI Implementation Polar Decoder using High Level Synthesis‏‎ (2 revisions)
9. Project Plan‏‎ (2 revisions)
10. Short Range Radars For Biomedical Application‏‎ (2 revisions)
11. Coding Guidelines‏‎ (2 revisions)
12. High Throughput Turbo Decoder Design‏‎ (2 revisions)
13. Development Of A Test Bed For Ultrasonic Transducer Characterization‏‎ (2 revisions - redirect page)
14. Autonomous Smart Sensors for IoT‏‎ (2 revisions - redirect page)
15. Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)‏‎ (2 revisions)
16. Towards Self-Sustainable Unmanned Aerial Vehicles‏‎ (2 revisions)
17. Hardware Support for IDE in Multicore Environment‏‎ (2 revisions)
18. PULP Freertos with LLVM‏‎ (2 revisions)
19. Wearables for Sports and Life Enhancement‏‎ (2 revisions)
20. EvaLTE: A 2G/3G/4G Cellular Transceiver FMC‏‎ (2 revisions)
21. An Efficient Compiler Backend for Snitch (1S/B)‏‎ (2 revisions)
22. Reconfigurability of SHA-3 candidates‏‎ (2 revisions)
23. Audio Visual Speech Recognition (1S/1M)‏‎ (2 revisions)
24. Event-based navigation on autonomous nano-drones‏‎ (2 revisions)
25. Time Synchronization for 3G Mobile Communications‏‎ (2 revisions)
26. Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing‏‎ (2 revisions)
27. Integrating Hardware Accelerators into Snitch 1S‏‎ (2 revisions - redirect page)
28. Flexible Front-End Circuit for Biomedical Data Acquisition‏‎ (2 revisions)
29. Computation of Phonon Bandstructure in III-V Nanostructures‏‎ (2 revisions)
30. Design of a Low Power Smart Sensing Multi-modal Vision Platform‏‎ (2 revisions)
31. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (2 revisions)
32. Securing Block Ciphers against SCA and SIFA‏‎ (2 revisions)
33. Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA‏‎ (2 revisions)
34. Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs‏‎ (2 revisions)
35. Coherence-Capable Write-Back L1 Data Cache for Ariane (M)‏‎ (2 revisions)
36. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (2 revisions)
37. Mixed Signal IC Design‏‎ (2 revisions)
38. Herschmi‏‎ (2 revisions)
39. Softmax for Transformers (M/1-2S)‏‎ (2 revisions)
40. Neural Architecture Search using Reinforcement Learning and Search Space Reduction‏‎ (2 revisions)
41. Design of low mismatch DAC used for VAD‏‎ (2 revisions)
42. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision‏‎ (2 revisions)
43. DaCe on Snitch‏‎ (2 revisions)
44. Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)‏‎ (2 revisions)
45. Analog Layout Engine‏‎ (2 revisions)
46. Autonomus Drones With Novel Sensors And Ultra Wide Band‏‎ (2 revisions)
47. Heterogeneous Acceleration Systems‏‎ (2 revisions - redirect page)
48. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)‏‎ (2 revisions)
49. Improving Cold-Start in Batteryless And Energy Harvesting Systems‏‎ (2 revisions)
50. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)‏‎ (2 revisions)

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