Pages with the fewest revisions

Showing below up to 50 results in range #1 to #50.

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)

1. High Performance Cellular Receivers in Very Advanced CMOS‏‎ (2 revisions)
2. Implementation of a 2-D model for Li-ion batteries‏‎ (2 revisions)
3. Benchmarking a heterogeneous 217-core MPSoC on HPC applications‏‎ (2 revisions)
4. Smart Patch For Heath Care And Rehabilitation‏‎ (2 revisions)
5. A Post-Simulation Trace-Based RISC-V GDB Debugging Server‏‎ (2 revisions)
6. Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings‏‎ (2 revisions)
7. Accelerators for object detection and tracking‏‎ (2 revisions)
8. Test project‏‎ (2 revisions)
9. Triple-Core PULPissimo‏‎ (2 revisions)
10. Deep Unfolding of Iterative Optimization Algorithms‏‎ (2 revisions)
11. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks‏‎ (2 revisions)
12. An Efficient Compiler Backend for Snitch (1S/B)‏‎ (2 revisions)
13. Successive Interference Cancellation for 3G Downlink‏‎ (2 revisions)
14. System on Chips for IoTs‏‎ (2 revisions - redirect page)
15. Optimal System Duty Cycling‏‎ (2 revisions)
16. Accurate deep learning inference using computational memory‏‎ (2 revisions)
17. Quantum Transport Modeling of Interband Cascade Lasers (ICL)‏‎ (2 revisions)
18. Autonomous Smart Sensors for IoT‏‎ (2 revisions - redirect page)
19. BirdGuard‏‎ (2 revisions)
20. Mixed Signal IC Design‏‎ (2 revisions)
21. Data Mapping for Unreliable Memories‏‎ (2 revisions)
22. High-Resolution, Calibrated Folding ADCs‏‎ (2 revisions)
23. PREM Intervals and Loop Tiling‏‎ (2 revisions)
24. Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)‏‎ (2 revisions)
25. Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA‏‎ (2 revisions)
26. AXI-based Network on Chip (NoC) system‏‎ (2 revisions)
27. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)‏‎ (2 revisions)
28. Audio Visual Speech Recognition (1S/1M)‏‎ (2 revisions)
29. Kinetic Energy Harvesting For Autonomous Smart Watches‏‎ (2 revisions)
30. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))‏‎ (2 revisions)
31. Low Precision Ara for ML‏‎ (2 revisions)
32. Christoph Leitner‏‎ (2 revisions)
33. Development Of A Test Bed For Ultrasonic Transducer Characterization‏‎ (2 revisions - redirect page)
34. RazorEDGE‏‎ (2 revisions - redirect page)
35. Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon‏‎ (2 revisions)
36. Network-off-Chip (M)‏‎ (2 revisions)
37. Towards Flexible and Printable Wearables‏‎ (2 revisions)
38. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks‏‎ (2 revisions)
39. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)‏‎ (2 revisions)
40. Ab-initio Simulation of Strained Thermoelectric Materials‏‎ (2 revisions)
41. Wake Up Radio For Energy Efficient Communication System and IC Design‏‎ (2 revisions)
42. Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)‏‎ (2 revisions)
43. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP‏‎ (2 revisions)
44. Design of low mismatch DAC used for VAD‏‎ (2 revisions)
45. Adaptively Controlled Hysteresis Curve Tracer For Polymer Piezoelectrics (1 S/B)‏‎ (2 revisions - redirect page)
46. Research‏‎ (2 revisions)
47. Evaluating memory access pattern specializations in OoO, server-grade cores (M)‏‎ (2 revisions)
48. Short Range Radars For Biomedical Application‏‎ (2 revisions)
49. Low Resolution Neural Networks‏‎ (2 revisions)
50. Norbert Felber‏‎ (2 revisions)

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)