Upload log
From iis-projects
Below is a list of the most recent file uploads. See the gallery of new files for a more visual overview.
(newest | oldest) View (newer 20 | older 20) (20 | 50 | 100 | 250 | 500)- 17:22, 4 February 2014 Gautschi (talk | contribs) uploaded File:Fpudesign.jpg
- 17:20, 4 February 2014 Gautschi (talk | contribs) uploaded a new version of File:Ultra-low power processor design.jpg (Reverted to version as of 09:11, 16 January 2014)
- 17:19, 4 February 2014 Gautschi (talk | contribs) uploaded a new version of File:Ultra-low power processor design.jpg
- 10:39, 4 February 2014 Kgf (talk | contribs) uploaded File:Data Mapping for Unreliable Memories.png (Top: Digital communication system employing BPSK transmission over an AWGN channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations.)
- 10:33, 4 February 2014 Kgf (talk | contribs) uploaded File:Exploitation of Inherent Error Resilience of Wireless Systems.png (Top: Simplified block diagram of the considered 3GPP TD-HSPA wireless communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates.)
- 10:24, 4 February 2014 Kgf (talk | contribs) uploaded File:High Throughput Turbo Decoder Design.png (Chip micrograph of the LTE-Advanced turbo decoder. The overlay depicts the exact locations of the 16 parallel SISO decoders used to achieve the 1Gbps throughput.)
- 10:18, 4 February 2014 Kgf (talk | contribs) uploaded File:Turbo Decoder Design for High Code Rates.png (The impact of code rate on throughput and memory capacity of traditional acquisition-run-based turbo decoders (ATD) and state-metric-propagation-based turbo decoder implementations (STD).)
- 10:10, 4 February 2014 Kgf (talk | contribs) uploaded File:Channel Decoding for TD-HSPA.png (Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.)
- 18:01, 30 January 2014 Kgf (talk | contribs) uploaded File:Progressive grouping stage with MLD pruning.png (A tree portion of the progressive grouping stage with MLD pruning, which is used in the pre-processing step in a low-complexity sequence detector.)
- 17:47, 30 January 2014 Kgf (talk | contribs) uploaded File:Block diagram of the LEG-CVA receiver.png (Top: A block diagram of the LEG-CVA receiver. Bottom: Modem Bit-Error-Rate vs. Received Signal-to-Noise Power Ratio for TD-HSPA, Case-3 Multipath Channel, 16-CDMA codes and 64-QAM.)
- 17:27, 30 January 2014 Kgf (talk | contribs) uploaded File:Successive interference cancellation multi user detector.png (Performance of the successive interference cancellation multi user detector (SIC-MUD) and the corresponding hardware implementation compared to the traditional linear MMSE equalizer.)
- 17:21, 30 January 2014 Kgf (talk | contribs) uploaded File:Basic working principle of the Steiner channel estimator.png (Basic working principle of the Steiner channel estimator)
- 17:11, 30 January 2014 Kgf (talk | contribs) uploaded File:High-level dedicated IR architecture storing punctured RLC blocks.png (Top: Simulation results for coding schemes MCS-9 and DAS-12 in order to evalute IR performance. Bottom: High-level dedicated IR architecture storing punctured RLC blocks.)
- 17:04, 30 January 2014 Kgf (talk | contribs) uploaded File:Setup of OsmoPHY together with RX board.png (Top: Software architecture of the OsmoPHY framework. Bottom: Setup of OsmoPHY together with RX board, OsmocomBB and wireshark0 protocol analyzer.)
- 18:32, 29 January 2014 Kgf (talk | contribs) uploaded File:Block diagram of the space-time interference canceller.png (Top: Interference scenario in cellular radio. Center: Layout of the RazorEDGE baseband ASIC Bottom: Block diagram of the space-time interference canceller.)
- 18:26, 29 January 2014 Kgf (talk | contribs) uploaded File:Simplified trellis as used in the SOVE algorithm.png (Top: Simplified trellis as used in the SOVE algorithm. Bottom: Layout of the RazorEDGE physical layer baseband ASIC. The highlighted area is occupied by the SOVE block.)
- 18:15, 29 January 2014 Kgf (talk | contribs) uploaded File:Battery powered medical signal acquisition platform.png
- 18:01, 29 January 2014 Kgf (talk | contribs) uploaded File:Chip Micrograph of Cerebrov2.png (Chip micrograph of the 8-channel sensor front-end and data acquisition IC ‘Cerebro v2’ for electrode-based medical applications, such as ECG or EEG. Implemented in a 130 nm CMOS technology.)
- 17:52, 29 January 2014 Kgf (talk | contribs) uploaded File:Direcdt conversion receiver topology.png (A direct-conversion receiver topology often used for cellular receiver, due to its good configurability.)
- 17:46, 29 January 2014 Kgf (talk | contribs) uploaded File:Baseband filter transfer functions.png (Measured baseband filter transfer functions, demonstrating the flat transfer function and the wide range of programmability in terms of frequency and gain.)