Upload log
From iis-projects
Below is a list of the most recent file uploads. See the gallery of new files for a more visual overview.
(newest | oldest) View (newer 20 | older 20) (20 | 50 | 100 | 250 | 500)- 17:27, 30 January 2014 Kgf (talk | contribs) uploaded File:Successive interference cancellation multi user detector.png (Performance of the successive interference cancellation multi user detector (SIC-MUD) and the corresponding hardware implementation compared to the traditional linear MMSE equalizer.)
- 17:21, 30 January 2014 Kgf (talk | contribs) uploaded File:Basic working principle of the Steiner channel estimator.png (Basic working principle of the Steiner channel estimator)
- 17:11, 30 January 2014 Kgf (talk | contribs) uploaded File:High-level dedicated IR architecture storing punctured RLC blocks.png (Top: Simulation results for coding schemes MCS-9 and DAS-12 in order to evalute IR performance. Bottom: High-level dedicated IR architecture storing punctured RLC blocks.)
- 17:04, 30 January 2014 Kgf (talk | contribs) uploaded File:Setup of OsmoPHY together with RX board.png (Top: Software architecture of the OsmoPHY framework. Bottom: Setup of OsmoPHY together with RX board, OsmocomBB and wireshark0 protocol analyzer.)
- 18:32, 29 January 2014 Kgf (talk | contribs) uploaded File:Block diagram of the space-time interference canceller.png (Top: Interference scenario in cellular radio. Center: Layout of the RazorEDGE baseband ASIC Bottom: Block diagram of the space-time interference canceller.)
- 18:26, 29 January 2014 Kgf (talk | contribs) uploaded File:Simplified trellis as used in the SOVE algorithm.png (Top: Simplified trellis as used in the SOVE algorithm. Bottom: Layout of the RazorEDGE physical layer baseband ASIC. The highlighted area is occupied by the SOVE block.)
- 18:15, 29 January 2014 Kgf (talk | contribs) uploaded File:Battery powered medical signal acquisition platform.png
- 18:01, 29 January 2014 Kgf (talk | contribs) uploaded File:Chip Micrograph of Cerebrov2.png (Chip micrograph of the 8-channel sensor front-end and data acquisition IC ‘Cerebro v2’ for electrode-based medical applications, such as ECG or EEG. Implemented in a 130 nm CMOS technology.)
- 17:52, 29 January 2014 Kgf (talk | contribs) uploaded File:Direcdt conversion receiver topology.png (A direct-conversion receiver topology often used for cellular receiver, due to its good configurability.)
- 17:46, 29 January 2014 Kgf (talk | contribs) uploaded File:Baseband filter transfer functions.png (Measured baseband filter transfer functions, demonstrating the flat transfer function and the wide range of programmability in terms of frequency and gain.)
- 17:38, 29 January 2014 Kgf (talk | contribs) uploaded File:Measured high resolution folding ADC.png (Left: Measured output spectrum of a sinusoidal input signal at 60.123 MHz sampled at 150 MHz. Right: Chip micrograph of the implemented ADC in 130 nm CMOS.)
- 17:28, 29 January 2014 Kgf (talk | contribs) uploaded File:Simulated spectrum of high resolution large bw.png (Simulated spectrum at the output of the modulator for a sinusoidal input signal at 40MHz.)
- 18:49, 28 January 2014 Kgf (talk | contribs) uploaded a new version of File:AMP OMP block diagram.png
- 18:47, 28 January 2014 Kgf (talk | contribs) uploaded File:AMP OMP block diagram.png
- 18:35, 28 January 2014 Kgf (talk | contribs) uploaded File:Sandstorm layout.png
- 18:28, 28 January 2014 Kgf (talk | contribs) uploaded File:Madmax explanations.png
- 18:16, 28 January 2014 Kgf (talk | contribs) uploaded File:Warping example.png (Aspect ratio retargeting example illustrating the image domain warping steps: from an initial regular grid, we generate a spatially-varying warp grid that is used to warp the image. Original image: Courtesy of Andrew Malone (CC).)
- 17:21, 28 January 2014 Kgf (talk | contribs) uploaded File:Serpent high throughput.png (Block diagram illustrating the OCB-Serpent architecture with four fully-unrolled Serpent cores.)
- 17:10, 28 January 2014 Kgf (talk | contribs) uploaded File:3D board of qcrypt.png (This picture shows a 3D model of the new version of the PCB. All network connections are now located on the top side of the board, making it suitable for dense housing in racks.)
- 16:29, 28 January 2014 Kgf (talk | contribs) uploaded File:Graestl.png (Top: FPGA floorplan containing the microprocessor and the GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, hosting a separate AES/Grøstl design and GrÆStl.)