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- (M): A Flexible Peripheral System for High-Performance Systems on Chip
- 3D Matrix Multiplication Unit for ITA (1S)
- 3D Ultrasound Bubble Tracking
- 4th Generation Synchronization
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- AMZ Driverless Competition Embedded Systems Projects
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of Jammer Mitigation
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
- ASIC implementation of an interpolation-based wideband massive MIMO detector
- ASR-Waveformer
- AXI-based Network on Chip (NoC) system
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A Post-Simulation Trace-Based RISC-V GDB Debugging Server
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Snitch-based Compute Accelerator for HERO
- A Trustworthy Three-Factor Authentication System
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for HPC monitoring
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A computational memory unit using phase-change memory devices
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- Ab-initio Simulation of Strained Thermoelectric Materials
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Accelerators for object detection and tracking
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Advanced 5G Repetition Combining
- Advanced Data Movers for Modern Neural Networks
- Advanced EEG glasses
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Alias-Free Oscillator Synchronization for Arbitrary Waveforms
- Aliasing-Free Wavetable Music Synthesizer
- All the flavours of FFT on MemPool (1-2S/B)
- Ambient RF Energy harvesting for Wireless Sensor Network
- An Efficient Compiler Backend for Snitch (1S/B)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Evaluation Platform for Mobile Communications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- AnalogInt
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analog Layout Engine
- Analog building blocks for mmWave manipulation
- Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
- Android Software Design
- Android reliability governor
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Artificial Reverberation for Embedded Systems
- Assessment of novel photovoltaic architectures by circuit simulation
- Audio DAC Conversion Jitter Measurement System
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Automatic unplugging detection for Ultrasound probes
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- BCI-controlled Drone
- BLISS - Battery-Less Identification System for Security
- Bandwidth Efficient NEureka
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
- Bateryless Heart Rate Monitoring
- Battery indifferent wearable Ultrasound
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Beat Cadence
- Beat DigRF
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Big Data Analytics Benchmarks for Ara
- Biomedical Systems on Chip
- BirdGuard
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Bluetooth Low Energy network with optimized data throughput
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Brunn test
- Build the Fastest 2G Modem Ever
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- CPS Software-Configurable State-Machine
- Cell-Free mmWave Massive MIMO Communication
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 3GPP TD-SCDMA
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Channel Estimation for TD-HSPA
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- Charge and heat transport through graphene nanoribbon based devices
- Charging System for Implantable Electronics
- Circuits and Systems for Nanoelectrode Array Biosensors
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing for Wireless Biosignal Monitoring
- Compression of Ultrasound data on FPGA
- Compression of iEEG Data
- Computation of Phonon Bandstructure in III-V Nanostructures
- Configurable Ultra Low Power LDO
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating a HDMI Video Interface for PULP
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cycle-Accurate Event-Based Simulation of Snitch Core
- DC-DC Buck converter in 65nm CMOS
- DaCe on Snitch
- Data Augmentation Techniques in Biosignal Classification
- Data Mapping for Unreliable Memories
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Deep Unfolding of Iterative Optimization Algorithms
- Deep neural networks for seizure detection
- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of ultra low power vision system
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Design of MEMs Sensor Interface
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- Design of State Retentive Flip-Flops
- Design of Streaming Data Platform for High-Speed ADC Data
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a Fused Multiply Add Floating Point Unit
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
- Design of a VLIW processor architecture based on RISC-V
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an LTE Module for the Internet of Things
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of combined Ultrasound and Electromyography systems
- Design of combined Ultrasound and PPG systems
- Design of low-offset dynamic comparators
- Design of low mismatch DAC used for VAD
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Design study of tunneling transistors based on a core/shell nanowire structures
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Designing a Power Management Unit for PULP SoCs
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing High Efficiency Batteries for Electric Cars
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Development of a Rockfall Sensor Node
- Development of a fingertip blood pressure sensor
- Development of a syringe label reader for the neurocritical care unit
- Development of an efficient algorithm for quantum transport codes
- Development of an implantable Force sensor for orthopedic applications
- Development of statistics and contention monitoring unit for PULP
- DigitalUltrasoundHead
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Control of a DC/DC Buck Converter
- Digital Transmitter for Cellular IoT
- Digitally-Controlled Analog Subtractive Sound Synthesis
- EEG-based drowsiness detection
- EEG artifact detection for epilepsy monitoring
- EEG artifact detection with machine learning
- EEG earbud
- Edge Computing for Long-Term Wearable Biomedical Systems
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Search Design for Hyperdimensional Computing
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN Inference on PULP Systems
- Efficient TNN compression
- Efficient collective communications in FlooNoC (1M)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Elliptic Curve Accelerator for zkSNARKs
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Efficient Systolic Execution on MemPool (M)
- Enabling Standalone Operation
- Enabling Standalone Operation for a Mobile Health Platform
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Engineering For Kids
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- FFT-based Convolutional Network Accelerator
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
- FPGA mapping of RPC DRAM
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Finite Element Simulations of Transistors for Quantum Computing
- Finite element modeling of electrochemical random access memory
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- Forward error-correction ASIC using GRAND
- Freedom from Interference in Heterogeneous COTS SoCs
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- GPT on the edge
- GRAND Hardware Implementation
- GSM Voice Capacity Evolution - VAMOS
- GUI-developement for an action-cam-based eye tracking device
- Glitches Reduce Listening Time of Your iPod
- Gomeza old project1
- Gomeza old project2
- Gomeza old project3
- Gomeza old project4
- Gomeza old project5
- Graph neural networks for epileptic seizure detection
- HERO: TLB Invalidation
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Hardware Accelerated Derivative Pricing
- Hardware Acceleration
- Hardware Accelerator Integration into Embedded Linux
- Hardware Accelerator for Model Predictive Controller
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Herschmi
- High-Resolution, Calibrated Folding ADCs
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- High-speed Scene Labeling on FPGA
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High Performance Cellular Receivers in Very Advanced CMOS
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hypervisor Extension for Ariane (M)
- IBM A2O Core
- IBM Research–Zurich
- IP-Based SoC Generation and Configuration (1-3S)
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (1M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Image Sensor Interface and Pre-processing
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Implementation of a 2-D model for Li-ion batteries
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Improving our Smart Camera System
- In-ear EEG signal acquisition
- Indoor Positioning with Bluetooth
- Indoor Smart Tracking of Hospital instrumentation
- Inductive Charging Circuit for Implantable Devices
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Infrared Wake Up Radio
- Integrated silicon photonic structures
- Integrated silicon photonic structures-Lumiphase
- Integrating Hardware Accelerators into Snitch
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Interference Cancellation for the cellular Internet of Things
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Investigation of the source starvation effect in III-V MOSFET
- IoT Turbo Decoder
- Jammer-Resilient Synchronization for Wireless Communications
- Jammer Mitigation Meets Machine Learning
- Kinetic Energy Harvesting For Autonomous Smart Watches
- Knowledge Distillation for Embedded Machine Learning
- LAPACK/BLAS for FPGA
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
- LTE IoT Network Synchronization
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Learning at the Edge with Hardware-Aware Algorithms
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Libria
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - CNN-Based-Image-Reconstruction
- LightProbe - Design of a High-Speed Optical Link
- LightProbe - Frontend Firmware and Control Side Channel
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - Thermal-Power aware on-head Beamforming
- LightProbe - Ultracompact Power Supply PCB
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Low-Complexity MIMO Detection
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Power Time Synchronization for IoT Applications
- Low-Resolution 5G Beamforming Codebook Design
- Low-power Clock Generation Solutions for 65nm Technology
- Low-power Temperature-insensitive Timer
- Low-power chip-to-chip communication network
- Low-power time synchronization for IoT applications
- Low Latency Brain-Machine Interfaces
- Low Power Embedded Systems and Wireless Sensors Networks
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Precision Ara for ML
- Low Resolution Neural Networks
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Machine Learning on Ultrasound Images
- Main Page
- Make Cellular Internet of Things Receivers Smart
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Matheus Cavalcante
- Mattia
- MemPool on HERO
- MemPool on HERO (1S)
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Minimal Cost RISC-V core
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Modeling FlooNoC in GVSoC (S/M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Modular Distributed Data Collection Platform
- Modular Frequency-Modulation (FM) Music Synthesizer
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Moritz Schneider
- Multi-Band Receiver Design for LTE Mobile Communication
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
- NAND Flash Open Research Platform
- NORX - an AEAD algorithm for the CAESAR competition
- NVDLA meets PULP
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Near-Memory Training of Neural Networks
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neural Processing
- Neural Recording Interface and Signal Processing
- Neural Recording Interface and Spike Sorting Algorithm
- NeuroSoC RISC-V Component (M/1-2S)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- NextGenChannelDec
- Next Generation Synchronization Signals
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- Object Detection and Tracking on the Edge
- On-Board Software for PULP on a Satellite
