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Showing below up to 50 results in range #1 to #50.

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  1. (hist) ‎Energy Efficient Autonomous UAVs ‎[14,635 bytes]
  2. (hist) ‎Human Intranet ‎[13,462 bytes]
  3. (hist) ‎Transforming MemPool into a CGRA (M) ‎[13,059 bytes]
  4. (hist) ‎Efficient Synchronization of Manycore Systems (M/1S) ‎[12,563 bytes]
  5. (hist) ‎Deep Learning Projects ‎[12,273 bytes]
  6. (hist) ‎Feature Extraction for Speech Recognition (1S) ‎[11,895 bytes]
  7. (hist) ‎A Flexible Peripheral System for High-Performance Systems on Chip (M) ‎[11,717 bytes]
  8. (hist) ‎Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) ‎[11,255 bytes]
  9. (hist) ‎A Snitch-based Compute Accelerator for HERO (M/1-2S) ‎[11,101 bytes]
  10. (hist) ‎LLVM and DaCe for Snitch (1-2S) ‎[11,092 bytes]
  11. (hist) ‎Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) ‎[11,007 bytes]
  12. (hist) ‎Online Learning of User Features (1S) ‎[10,880 bytes]
  13. (hist) ‎Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) ‎[10,771 bytes]
  14. (hist) ‎Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) ‎[10,534 bytes]
  15. (hist) ‎PULP ‎[10,511 bytes]
  16. (hist) ‎Ultra-low power processor design ‎[10,511 bytes]
  17. (hist) ‎Implementing DSP Instructions in Banshee (1S) ‎[10,116 bytes]
  18. (hist) ‎IBM Research ‎[10,064 bytes]
  19. (hist) ‎Hyperdimensional Computing ‎[9,993 bytes]
  20. (hist) ‎Fast Simulation of Manycore Systems (1S) ‎[9,741 bytes]
  21. (hist) ‎Bringing XNOR-nets (ConvNets) to Silicon ‎[9,740 bytes]
  22. (hist) ‎Graph neural networks for epileptic seizure detection ‎[9,729 bytes]
  23. (hist) ‎High Performance SoCs ‎[9,290 bytes]
  24. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (M) ‎[9,151 bytes]
  25. (hist) ‎Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea ‎[9,139 bytes]
  26. (hist) ‎Design and Implementation of a Convolutional Neural Network Accelerator ASIC ‎[9,080 bytes]
  27. (hist) ‎Rethinking our Convolutional Network Accelerator Architecture ‎[9,007 bytes]
  28. (hist) ‎Heroino: Design of the next CORE-V Microcontroller ‎[8,937 bytes]
  29. (hist) ‎Manycore System on FPGA (M/S/G) ‎[8,654 bytes]
  30. (hist) ‎A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) ‎[8,380 bytes]
  31. (hist) ‎An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) ‎[8,317 bytes]
  32. (hist) ‎High-speed Scene Labeling on FPGA ‎[8,302 bytes]
  33. (hist) ‎Design of Scalable Event-driven Neural-Recording Digital Interface ‎[8,231 bytes]
  34. (hist) ‎MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. ‎[8,170 bytes]
  35. (hist) ‎FFT-based Convolutional Network Accelerator ‎[8,120 bytes]
  36. (hist) ‎Improved State Estimation on PULP-based Nano-UAVs ‎[8,098 bytes]
  37. (hist) ‎Improving our Smart Camera System ‎[8,056 bytes]
  38. (hist) ‎Practical Reconfigurable Intelligent Surfaces (RIS) ‎[7,975 bytes]
  39. (hist) ‎Floating-Point Divide & Square Root Unit for Transprecision ‎[7,966 bytes]
  40. (hist) ‎Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) ‎[7,927 bytes]
  41. (hist) ‎RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB ‎[7,824 bytes]
  42. (hist) ‎Mixed-Precision Neural Networks for Brain-Computer Interface Applications ‎[7,734 bytes]
  43. (hist) ‎Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) ‎[7,696 bytes]
  44. (hist) ‎Self-Supervised User Positioning in Cell-Free Massive MIMO Systems ‎[7,691 bytes]
  45. (hist) ‎Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) ‎[7,663 bytes]
  46. (hist) ‎Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs ‎[7,640 bytes]
  47. (hist) ‎XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory ‎[7,358 bytes]
  48. (hist) ‎Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications ‎[7,337 bytes]
  49. (hist) ‎Smart Patch For Heath Care And Rehabilitation ‎[7,308 bytes]
  50. (hist) ‎Cell-Free mmWave Massive MIMO Communication ‎[7,265 bytes]

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