Long pages
From iis-projects
Showing below up to 20 results in range #51 to #70.
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- (hist) Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs [8,002 bytes]
- (hist) Practical Reconfigurable Intelligent Surfaces (RIS) [7,979 bytes]
- (hist) Floating-Point Divide & Square Root Unit for Transprecision [7,966 bytes]
- (hist) Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) [7,927 bytes]
- (hist) RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB [7,824 bytes]
- (hist) GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) [7,808 bytes]
- (hist) Mixed-Precision Neural Networks for Brain-Computer Interface Applications [7,773 bytes]
- (hist) Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) [7,696 bytes]
- (hist) Self-Supervised User Positioning in Cell-Free Massive MIMO Systems [7,691 bytes]
- (hist) Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) [7,663 bytes]
- (hist) A RISC-V ISA Extension for Scalar Chaining in Snitch (M) [7,624 bytes]
- (hist) XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory [7,358 bytes]
- (hist) Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications [7,337 bytes]
- (hist) Smart Patch For Heath Care And Rehabilitation [7,308 bytes]
- (hist) Cell-Free mmWave Massive MIMO Communication [7,265 bytes]
- (hist) Weekly Reports [7,258 bytes]
- (hist) An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications [7,241 bytes]
- (hist) Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) [7,201 bytes]
- (hist) A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) [7,168 bytes]
- (hist) Baseband Meets CPU [7,100 bytes]
