Long pages
From iis-projects
Showing below up to 50 results in range #51 to #100.
View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)
- (hist) Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs [8,002 bytes]
- (hist) Practical Reconfigurable Intelligent Surfaces (RIS) [7,979 bytes]
- (hist) Floating-Point Divide & Square Root Unit for Transprecision [7,966 bytes]
- (hist) Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) [7,927 bytes]
- (hist) RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB [7,824 bytes]
- (hist) GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) [7,808 bytes]
- (hist) Mixed-Precision Neural Networks for Brain-Computer Interface Applications [7,773 bytes]
- (hist) Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) [7,696 bytes]
- (hist) Self-Supervised User Positioning in Cell-Free Massive MIMO Systems [7,691 bytes]
- (hist) Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) [7,663 bytes]
- (hist) A RISC-V ISA Extension for Scalar Chaining in Snitch (M) [7,661 bytes]
- (hist) XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory [7,358 bytes]
- (hist) Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications [7,337 bytes]
- (hist) Smart Patch For Heath Care And Rehabilitation [7,308 bytes]
- (hist) Cell-Free mmWave Massive MIMO Communication [7,265 bytes]
- (hist) Weekly Reports [7,258 bytes]
- (hist) An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications [7,241 bytes]
- (hist) Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) [7,201 bytes]
- (hist) A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) [7,168 bytes]
- (hist) Baseband Meets CPU [7,100 bytes]
- (hist) Towards Autonomous Navigation for Nano-Blimps [7,095 bytes]
- (hist) Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams [7,095 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) [7,075 bytes]
- (hist) Integrated Information Processing [7,051 bytes]
- (hist) Variable Bit Precision Logic for Deep Learning and Artificial Intelligence [6,993 bytes]
- (hist) Semi-Custom Digital VLSI for Processing-in-Memory [6,973 bytes]
- (hist) Digital [6,954 bytes]
- (hist) Hardware Acceleration [6,884 bytes]
- (hist) Bridging QuantLab with LPDNN [6,871 bytes]
- (hist) Evaluating memory access pattern specializations in OoO, server-grade cores (M) [6,859 bytes]
- (hist) ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G [6,834 bytes]
- (hist) Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores [6,805 bytes]
- (hist) On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA) [6,772 bytes]
- (hist) Single-Bit-Synapse Spiking Neural System-on-Chip [6,767 bytes]
- (hist) Accelerating Applications Relying on Matrix-Vector-Product-Like Operations [6,754 bytes]
- (hist) Learning at the Edge with Hardware-Aware Algorithms [6,742 bytes]
- (hist) Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core [6,724 bytes]
- (hist) Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets [6,711 bytes]
- (hist) Low Power Neural Network For Multi Sensors Wearable Devices [6,700 bytes]
- (hist) Multisensory system for performance analysis in ski jumping (M/1-2S/B) [6,642 bytes]
- (hist) Exploring NAS spaces with C-BRED [6,633 bytes]
- (hist) PULP in space - Fault Tolerant PULP System for Critical Space Applications [6,628 bytes]
- (hist) Hardware Accelerators for Lossless Quantized Deep Neural Networks [6,626 bytes]
- (hist) Improving Scene Labeling with Hyperspectral Data [6,596 bytes]
- (hist) Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration [6,550 bytes]
- (hist) Low-Resolution 5G Beamforming Codebook Design [6,549 bytes]
- (hist) Accelerating Matrix Multiplication on a 216-core MPSoC (1M) [6,535 bytes]
- (hist) Timing Channel Mitigations for RISC-V Cores [6,515 bytes]
- (hist) Serverless Benchmarks on RISC-V (M) [6,436 bytes]
- (hist) Investigation of Quantization Strategies for Retentive Networks (1S) [6,431 bytes]