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Showing below up to 50 results in range #51 to #100.

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51. (hist) ‎Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs ‎[8,002 bytes]
52. (hist) ‎Practical Reconfigurable Intelligent Surfaces (RIS) ‎[7,979 bytes]
53. (hist) ‎Floating-Point Divide & Square Root Unit for Transprecision ‎[7,966 bytes]
54. (hist) ‎Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) ‎[7,927 bytes]
55. (hist) ‎RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB ‎[7,824 bytes]
56. (hist) ‎GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) ‎[7,808 bytes]
57. (hist) ‎Mixed-Precision Neural Networks for Brain-Computer Interface Applications ‎[7,773 bytes]
58. (hist) ‎Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) ‎[7,696 bytes]
59. (hist) ‎Self-Supervised User Positioning in Cell-Free Massive MIMO Systems ‎[7,691 bytes]
60. (hist) ‎Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) ‎[7,663 bytes]
61. (hist) ‎A RISC-V ISA Extension for Scalar Chaining in Snitch (M) ‎[7,661 bytes]
62. (hist) ‎XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory ‎[7,358 bytes]
63. (hist) ‎Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications ‎[7,337 bytes]
64. (hist) ‎Smart Patch For Heath Care And Rehabilitation ‎[7,308 bytes]
65. (hist) ‎Cell-Free mmWave Massive MIMO Communication ‎[7,265 bytes]
66. (hist) ‎Weekly Reports ‎[7,258 bytes]
67. (hist) ‎An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications ‎[7,241 bytes]
68. (hist) ‎Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) ‎[7,201 bytes]
69. (hist) ‎A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) ‎[7,168 bytes]
70. (hist) ‎Baseband Meets CPU ‎[7,100 bytes]
71. (hist) ‎Towards Autonomous Navigation for Nano-Blimps ‎[7,095 bytes]
72. (hist) ‎Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams ‎[7,095 bytes]
73. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) ‎[7,075 bytes]
74. (hist) ‎Integrated Information Processing ‎[7,051 bytes]
75. (hist) ‎Variable Bit Precision Logic for Deep Learning and Artificial Intelligence ‎[6,993 bytes]
76. (hist) ‎Semi-Custom Digital VLSI for Processing-in-Memory ‎[6,973 bytes]
77. (hist) ‎Digital ‎[6,954 bytes]
78. (hist) ‎Hardware Acceleration ‎[6,884 bytes]
79. (hist) ‎Bridging QuantLab with LPDNN ‎[6,871 bytes]
80. (hist) ‎Evaluating memory access pattern specializations in OoO, server-grade cores (M) ‎[6,859 bytes]
81. (hist) ‎ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G ‎[6,834 bytes]
82. (hist) ‎Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores ‎[6,805 bytes]
83. (hist) ‎On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA) ‎[6,772 bytes]
84. (hist) ‎Single-Bit-Synapse Spiking Neural System-on-Chip ‎[6,767 bytes]
85. (hist) ‎Accelerating Applications Relying on Matrix-Vector-Product-Like Operations ‎[6,754 bytes]
86. (hist) ‎Learning at the Edge with Hardware-Aware Algorithms ‎[6,742 bytes]
87. (hist) ‎Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core ‎[6,724 bytes]
88. (hist) ‎Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets ‎[6,711 bytes]
89. (hist) ‎Low Power Neural Network For Multi Sensors Wearable Devices ‎[6,700 bytes]
90. (hist) ‎Multisensory system for performance analysis in ski jumping (M/1-2S/B) ‎[6,642 bytes]
91. (hist) ‎Exploring NAS spaces with C-BRED ‎[6,633 bytes]
92. (hist) ‎PULP in space - Fault Tolerant PULP System for Critical Space Applications ‎[6,628 bytes]
93. (hist) ‎Hardware Accelerators for Lossless Quantized Deep Neural Networks ‎[6,626 bytes]
94. (hist) ‎Improving Scene Labeling with Hyperspectral Data ‎[6,596 bytes]
95. (hist) ‎Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration ‎[6,550 bytes]
96. (hist) ‎Low-Resolution 5G Beamforming Codebook Design ‎[6,549 bytes]
97. (hist) ‎Accelerating Matrix Multiplication on a 216-core MPSoC (1M) ‎[6,535 bytes]
98. (hist) ‎Timing Channel Mitigations for RISC-V Cores ‎[6,515 bytes]
99. (hist) ‎Serverless Benchmarks on RISC-V (M) ‎[6,436 bytes]
100. (hist) ‎Investigation of Quantization Strategies for Retentive Networks (1S) ‎[6,431 bytes]

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