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Showing below up to 50 results in range #1 to #50.

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  1. Digital‏‎ (15 categories)
  2. BigPULP: Multicluster Synchronization Extensions‏‎ (14 categories)
  3. Smart Virtual Memory Sharing‏‎ (13 categories)
  4. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration‏‎ (13 categories)
  5. Manycore System on FPGA (M/S/G)‏‎ (13 categories)
  6. Hypervisor Extension for Ariane (M)‏‎ (13 categories)
  7. High-Speed Channel Estimation & Tracking for V2X Communications‏‎ (12 categories)
  8. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)‏‎ (12 categories)
  9. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)‏‎ (12 categories)
  10. Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design‏‎ (12 categories)
  11. High-Throughput Channel Coding & Decoding for V2X Communications‏‎ (12 categories)
  12. Streaming Integer Extensions for Snitch (M/1-2S)‏‎ (12 categories)
  13. Transforming MemPool into a CGRA (M)‏‎ (12 categories)
  14. Implementing DSP Instructions in Banshee (1S)‏‎ (12 categories)
  15. Real-Time ECG Contractions Classification‏‎ (12 categories)
  16. PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions‏‎ (12 categories)
  17. PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB‏‎ (12 categories)
  18. Baseband Meets CPU‏‎ (12 categories)
  19. PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker‏‎ (12 categories)
  20. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (11 categories)
  21. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)‏‎ (11 categories)
  22. Fast Accelerator Context Switch for PULP‏‎ (11 categories)
  23. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (11 categories)
  24. A Wireless Sensor Network for HPC monitoring‏‎ (11 categories)
  25. Memory Augmented Neural Networks in Brain-Computer Interfaces‏‎ (11 categories)
  26. Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers‏‎ (11 categories)
  27. CLIC for the CVA6‏‎ (11 categories)
  28. LLVM and DaCe for Snitch (1-2S)‏‎ (11 categories)
  29. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (11 categories)
  30. Efficient Synchronization of Manycore Systems (M/1S)‏‎ (11 categories)
  31. Creating a HDMI Video Interface for PULP‏‎ (11 categories)
  32. Non-blocking Algorithms in Real-Time Operating Systems‏‎ (11 categories)
  33. Efficient TNN Inference on PULP Systems‏‎ (11 categories)
  34. Minimum Variance Beamforming for Wearable Ultrasound Probes‏‎ (11 categories)
  35. BigPULP: Shared Virtual Memory Multicluster Extensions‏‎ (11 categories)
  36. Mixed-Precision Neural Networks for Brain-Computer Interface Applications‏‎ (11 categories)
  37. SCMI Support for Power Controller Subsystem‏‎ (11 categories)
  38. Compression of Ultrasound data on FPGA‏‎ (11 categories)
  39. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (11 categories)
  40. Integration and Implementation of Alibaba’s T-Head CLIC Interrupt Controller in PULP SoC‏‎ (10 categories)
  41. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (10 categories)
  42. An FPGA-Based Testbed for 3G Mobile Communications Receivers‏‎ (10 categories)
  43. IoT Turbo Decoder‏‎ (10 categories)
  44. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache‏‎ (10 categories)
  45. Visualizing Functional Microbubbles using Ultrasound Imaging‏‎ (10 categories)
  46. IP-Based SoC Generation and Configuration (1-3S/B)‏‎ (10 categories)
  47. Enabling Standalone Operation for a Mobile Health Platform‏‎ (10 categories)
  48. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (10 categories)
  49. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs‏‎ (10 categories)
  50. Shared Correlation Accelerator for an RF SoC‏‎ (10 categories)

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