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Showing below up to 100 results in range #1 to #100.

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  1. Wearable Ultrasound for Artery monitoring‏‎ (17 categories)
  2. Ultrasound-EMG combined hand gesture recognition‏‎ (16 categories)
  3. Design of combined Ultrasound and PPG systems‏‎ (16 categories)
  4. GPT on the edge‏‎ (15 categories)
  5. Digital‏‎ (15 categories)
  6. Towards Flexible and Printable Wearables‏‎ (15 categories)
  7. MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.‏‎ (14 categories)
  8. Ultrasound Doppler system development‏‎ (14 categories)
  9. Modular Distributed Data Collection Platform‏‎ (14 categories)
  10. Testbed Design for Self-sustainable IoT Sensors‏‎ (14 categories)
  11. BigPULP: Multicluster Synchronization Extensions‏‎ (14 categories)
  12. Resource Partitioning of RPC DRAM‏‎ (13 categories)
  13. Ultra low power wearable ultrasound probe‏‎ (13 categories)
  14. Manycore System on FPGA (M/S/G)‏‎ (13 categories)
  15. Battery indifferent wearable Ultrasound‏‎ (13 categories)
  16. Smart Virtual Memory Sharing‏‎ (13 categories)
  17. Advanced EEG glasses‏‎ (13 categories)
  18. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration‏‎ (13 categories)
  19. Hypervisor Extension for Ariane (M)‏‎ (13 categories)
  20. Design of combined Ultrasound and Electromyography systems‏‎ (13 categories)
  21. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems‏‎ (13 categories)
  22. Object Detection and Tracking on the Edge‏‎ (13 categories)
  23. Automatic unplugging detection for Ultrasound probes‏‎ (13 categories)
  24. Design of a Low Power Smart Sensing Multi-modal Vision Platform‏‎ (13 categories)
  25. Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs‏‎ (13 categories)
  26. FPGA mapping of RPC DRAM‏‎ (13 categories)
  27. Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models‏‎ (12 categories)
  28. PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker‏‎ (12 categories)
  29. Minimum Variance Beamforming for Wearable Ultrasound Probes‏‎ (12 categories)
  30. Efficient Synchronization of Manycore Systems (M/1S)‏‎ (12 categories)
  31. Real-Time ECG Contractions Classification‏‎ (12 categories)
  32. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)‏‎ (12 categories)
  33. Visualizing Functional Microbubbles using Ultrasound Imaging‏‎ (12 categories)
  34. Implementing DSP Instructions in Banshee (1S)‏‎ (12 categories)
  35. Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis‏‎ (12 categories)
  36. BCI-controlled Drone‏‎ (12 categories)
  37. Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets‏‎ (12 categories)
  38. Compression of Ultrasound data on FPGA‏‎ (12 categories)
  39. Ultrasound based hand gesture recognition‏‎ (12 categories)
  40. Streaming Integer Extensions for Snitch (M/1-2S)‏‎ (12 categories)
  41. PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions‏‎ (12 categories)
  42. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)‏‎ (12 categories)
  43. Baseband Meets CPU‏‎ (12 categories)
  44. Transforming MemPool into a CGRA (M)‏‎ (12 categories)
  45. PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB‏‎ (12 categories)
  46. Real-time Linux on RISC-V‏‎ (11 categories)
  47. Creating a HDMI Video Interface for PULP‏‎ (11 categories)
  48. Machine Learning on Ultrasound Images‏‎ (11 categories)
  49. Enabling Efficient Systolic Execution on MemPool (M)‏‎ (11 categories)
  50. Resource Partitioning of Caches‏‎ (11 categories)
  51. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)‏‎ (11 categories)
  52. BigPULP: Shared Virtual Memory Multicluster Extensions‏‎ (11 categories)
  53. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)‏‎ (11 categories)
  54. Event-based navigation on autonomous nano-drones‏‎ (11 categories)
  55. CLIC for the CVA6‏‎ (11 categories)
  56. Fast Accelerator Context Switch for PULP‏‎ (11 categories)
  57. EEG-based drowsiness detection‏‎ (11 categories)
  58. Mixed-Precision Neural Networks for Brain-Computer Interface Applications‏‎ (11 categories)
  59. Non-blocking Algorithms in Real-Time Operating Systems‏‎ (11 categories)
  60. Predict eye movement through brain activity‏‎ (11 categories)
  61. Development of statistics and contention monitoring unit for PULP‏‎ (11 categories)
  62. Routing 1000s of wires in Network-on-Chips (1-2S/M)‏‎ (11 categories)
  63. Modeling FlooNoC in GVSoC (S/M)‏‎ (11 categories)
  64. LLVM and DaCe for Snitch (1-2S)‏‎ (11 categories)
  65. Running Rust on PULP‏‎ (11 categories)
  66. Smart e-glasses for concealed recording of EEG signals‏‎ (11 categories)
  67. EEG earbud‏‎ (11 categories)
  68. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)‏‎ (11 categories)
  69. Evaluating SoA Post-Training Quantization Algorithms‏‎ (11 categories)
  70. In-ear EEG signal acquisition‏‎ (11 categories)
  71. A Wireless Sensor Network for HPC monitoring‏‎ (11 categories)
  72. Fault-Tolerant Floating-Point Units (M)‏‎ (11 categories)
  73. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (11 categories)
  74. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration‏‎ (11 categories)
  75. SCMI Support for Power Controller Subsystem‏‎ (11 categories)
  76. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (11 categories)
  77. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)‏‎ (11 categories)
  78. Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers‏‎ (11 categories)
  79. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (11 categories)
  80. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)‏‎ (11 categories)
  81. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)‏‎ (11 categories)
  82. Memory Augmented Neural Networks in Brain-Computer Interfaces‏‎ (11 categories)
  83. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (11 categories)
  84. Time Gain Compensation for Ultrasound Imaging‏‎ (11 categories)
  85. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)‏‎ (11 categories)
  86. Ibex: Tightly-Coupled Accelerators and ISA Extensions‏‎ (10 categories)
  87. Smart Meters‏‎ (10 categories)
  88. Enhancing our DMA Engine with Fault Tolerance‏‎ (10 categories)
  89. Graph neural networks for epileptic seizure detection‏‎ (10 categories)
  90. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)‏‎ (10 categories)
  91. A Unified Compute Kernel Library for Snitch (1-2S)‏‎ (10 categories)
  92. Multi issue OoO Ariane Backend (M)‏‎ (10 categories)
  93. Shared Correlation Accelerator for an RF SoC‏‎ (10 categories)
  94. Extend the RI5CY core with priviledge extensions‏‎ (10 categories)
  95. Big Data Analytics Benchmarks for Ara‏‎ (10 categories)
  96. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (10 categories)
  97. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory‏‎ (10 categories)
  98. Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)‏‎ (10 categories)
  99. An FPGA-Based Testbed for 3G Mobile Communications Receivers‏‎ (10 categories)
  100. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (10 categories)

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