Pages with the most categories
From iis-projects
Showing below up to 100 results in range #51 to #150.
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- Enabling Efficient Systolic Execution on MemPool (M) (11 categories)
- BigPULP: Shared Virtual Memory Multicluster Extensions (11 categories)
- Resource Partitioning of Caches (11 categories)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (11 categories)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (11 categories)
- Event-based navigation on autonomous nano-drones (11 categories)
- CLIC for the CVA6 (11 categories)
- Fast Accelerator Context Switch for PULP (11 categories)
- EEG-based drowsiness detection (11 categories)
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications (11 categories)
- Non-blocking Algorithms in Real-Time Operating Systems (11 categories)
- Predict eye movement through brain activity (11 categories)
- Development of statistics and contention monitoring unit for PULP (11 categories)
- Routing 1000s of wires in Network-on-Chips (1-2S/M) (11 categories)
- Modeling FlooNoC in GVSoC (S/M) (11 categories)
- LLVM and DaCe for Snitch (1-2S) (11 categories)
- Running Rust on PULP (11 categories)
- Smart e-glasses for concealed recording of EEG signals (11 categories)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (11 categories)
- A Wireless Sensor Network for HPC monitoring (11 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration (11 categories)
- EEG earbud (11 categories)
- Evaluating SoA Post-Training Quantization Algorithms (11 categories)
- Fault-Tolerant Floating-Point Units (M) (11 categories)
- In-ear EEG signal acquisition (11 categories)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (11 categories)
- SCMI Support for Power Controller Subsystem (11 categories)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (11 categories)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (11 categories)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (11 categories)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (11 categories)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers (11 categories)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) (11 categories)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (11 categories)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (11 categories)
- Streaming Layer Normalization in ITA (M/1-2S) (10 categories)
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings (10 categories)
- Zephyr RTOS on PULP (10 categories)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (10 categories)
- Deep Learning-based Global Local Planner for Autonomous Nano-drones (10 categories)
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) (10 categories)
- Next Generation Synchronization Signals (10 categories)
- A Unified Compute Kernel Library for Snitch (1-2S) (10 categories)
- Ibex: Tightly-Coupled Accelerators and ISA Extensions (10 categories)
- Smart Meters (10 categories)
- Enhancing our DMA Engine with Fault Tolerance (10 categories)
- Graph neural networks for epileptic seizure detection (10 categories)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (10 categories)
- Multi issue OoO Ariane Backend (M) (10 categories)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (10 categories)
- Shared Correlation Accelerator for an RF SoC (10 categories)
- Extend the RI5CY core with priviledge extensions (10 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (10 categories)
- Big Data Analytics Benchmarks for Ara (10 categories)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (10 categories)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (10 categories)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (10 categories)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) (10 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (10 categories)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (10 categories)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (10 categories)
- Fast Simulation of Manycore Systems (1S) (10 categories)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (10 categories)
- Timing Channel Mitigations for RISC-V Cores (10 categories)
- Heroino: Design of the next CORE-V Microcontroller (10 categories)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) (10 categories)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (10 categories)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (10 categories)
- PULP’s CLIC extensions for fast interrupt handling (10 categories)
- BirdGuard (10 categories)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (10 categories)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (10 categories)
- Improving datarate and efficiency of ultra low power wearable ultrasound (10 categories)
- Efficient TNN Inference on PULP Systems (10 categories)
- Wireless Communication Systems for the IoT (10 categories)
- ASR-Waveformer (10 categories)
- Accelerator for Spatio-Temporal Video Filtering (10 categories)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (10 categories)
- GUI-developement for an action-cam-based eye tracking device (10 categories)
- Implementing Configurable Dual-Core Redundancy (10 categories)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (10 categories)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (10 categories)
- PULP Freertos with LLVM (10 categories)
- Data Augmentation Techniques in Biosignal Classification (10 categories)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (10 categories)
- IP-Based SoC Generation and Configuration (1-3S/B) (10 categories)
- Creating A Boundry Scan Generator (1-3S/B/2-3G) (10 categories)
- Ultrasound Low power WiFi with IMX7 (10 categories)
- Bridging QuantLab with LPDNN (10 categories)
- Improved Collision Avoidance for Nano-drones (10 categories)
- Softmax for Transformers (M/1-2S) (10 categories)
- IoT Turbo Decoder (10 categories)
- Watchdog Timer for PULP (10 categories)
- ISA extensions in the Snitch Processor for Signal Processing (M) (10 categories)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (10 categories)
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC (10 categories)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B) (10 categories)
- Machine Learning for extracting Muscle features from Ultrasound raw data (10 categories)
- PULPonFPGA: Hardware L2 Cache (10 categories)
- Floating-Point Divide & Square Root Unit for Transprecision (10 categories)
