Pages with the most revisions
From iis-projects
Showing below up to 100 results in range #1 to #100.
View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)
- Human Intranet (176 revisions)
- Digital Medical Ultrasound Imaging (176 revisions)
- Energy Efficient Autonomous UAVs (172 revisions)
- Deep Learning Projects (149 revisions)
- Main Page (128 revisions)
- Integrated Information Processing (127 revisions)
- PULP (108 revisions)
- Biomedical Circuits, Systems, and Applications (107 revisions)
- Digital (89 revisions)
- IBM Research (89 revisions)
- Biomedical System on Chips (69 revisions)
- Flexible Electronic Systems and Embedded Epidermal Devices (66 revisions)
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM (57 revisions)
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors (55 revisions)
- High Performance SoCs (53 revisions)
- Wearables for Sports and Fitness Tracking (52 revisions)
- Marco Bertuletti (50 revisions)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) (49 revisions)
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC (48 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (47 revisions)
- Brunn test (47 revisions)
- Quantum transport in 2D heterostructures (44 revisions)
- Template (43 revisions)
- Huawei Research (40 revisions)
- Real-Time Optical Flow Using Neural Networks (38 revisions)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (36 revisions)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B) (33 revisions)
- Hyperdimensional Computing (33 revisions)
- Real-Time ECG Contractions Classification (31 revisions)
- Analog (30 revisions)
- Probabilistic training algorithms for quantized neural networks (30 revisions)
- Design of Scalable Event-driven Neural-Recording Digital Interface (29 revisions)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B) (29 revisions)
- ASIC Development of 5G-NR LDPC Decoder (29 revisions)
- Andrea Cossettini (29 revisions)
- Energy Efficient Serial Link (28 revisions)
- Probing the limits of fake-quantised neural networks (27 revisions)
- Real-Time Embedded Systems (27 revisions)
- Exploring schedules for incremental and annealing quantization algorithms (26 revisions)
- Skin coupling media characterization for fitnesstracker applications (1 B/S) (25 revisions)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (24 revisions)
- Open Source Baseband Firmware for 2G Cellular Networks (24 revisions)
- Ultra-wideband Concurrent Ranging (24 revisions)
- Smart Meters (24 revisions)
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design (24 revisions)
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE (23 revisions)
- Real-Time Stereo to Multiview Conversion (22 revisions)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (21 revisions)
- Benjamin Weber (21 revisions)
- Low-Dropout Regulators for Magnetic Resonance Imaging (21 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration (20 revisions)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (20 revisions)
- Accelerator for Boosted Binary Features (20 revisions)
- Accelerator for Spatio-Temporal Video Filtering (20 revisions)
- Trace Debugger for custom RISC-V Core (19 revisions)
- Wireless Communication Systems for the IoT (19 revisions)
- PULP’s CLIC extensions for fast interrupt handling (19 revisions)
- 4th Generation Synchronization (19 revisions)
- FFT-based Convolutional Network Accelerator (19 revisions)
- Improving Scene Labeling with Hyperspectral Data (18 revisions)
- Flexfloat DL Training Framework (18 revisions)
- David J. Mack (18 revisions)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (18 revisions)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (18 revisions)
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE (18 revisions)
- Energy Efficient AXI Interface to Serial Link Physical Layer (17 revisions)
- Baseband Meets CPU (17 revisions)
- Fast Accelerator Context Switch for PULP (17 revisions)
- Streaming Integer Extensions for Snitch (M) (17 revisions - redirect page)
- Energy Efficient Circuits and IoT Systems Group (17 revisions)
- Compressed Sensing vs JPEG (17 revisions)
- BLISS - Battery-Less Identification System for Security (17 revisions)
- A Snitch-based Compute Accelerator for HERO (17 revisions)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (17 revisions)
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs (17 revisions)
- Optimal System Duty Cycling for a Mobile Health Platform (16 revisions)
- LightProbe (16 revisions)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (16 revisions)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (16 revisions)
- 3D Turbo Decoder ASIC Realization (16 revisions)
- Rethinking our Convolutional Network Accelerator Architecture (16 revisions)
- Heterogeneous SoCs (16 revisions)
- Completed (15 revisions)
- Active-Set QP Solver on FPGA (15 revisions)
- Digital Transmitter for Mobile Communications (15 revisions)
- PULP-Shield for Autonomous UAV (15 revisions)
- Vector Processor for In-Memory Computing (15 revisions)
- Big Data Analytics Benchmarks for Ara (15 revisions)
- Elliptic Curve Accelerator for zkSNARKs (15 revisions)
- Digital Beamforming for Ultrasound Imaging (15 revisions)
- DMA Streaming Co-processor (15 revisions)
- Design of an LTE Module for the Internet of Things (15 revisions)
- Advanced 5G Repetition Combining (15 revisions)
- Ultra low power wearable ultrasound probe (14 revisions)
- Application Specific Frequency Synthesizers (Analog/Digital PLLs) (14 revisions)
- ASIC Design of a Gaussian Message Passing Processor (14 revisions)
- HW/SW Safety and Security (14 revisions)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (14 revisions)
- Beamspace processing for 5G mmWave massive MIMO on GPU (14 revisions)
- Heroino: Design of the next CORE-V Microcontroller (14 revisions)