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Showing below up to 50 results in range #51 to #100.

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51. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration‏‎ (20 revisions)
52. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA‏‎ (20 revisions)
53. Accelerator for Boosted Binary Features‏‎ (20 revisions)
54. Accelerator for Spatio-Temporal Video Filtering‏‎ (20 revisions)
55. FFT-based Convolutional Network Accelerator‏‎ (19 revisions)
56. Trace Debugger for custom RISC-V Core‏‎ (19 revisions)
57. Wireless Communication Systems for the IoT‏‎ (19 revisions)
58. PULP’s CLIC extensions for fast interrupt handling‏‎ (19 revisions)
59. 4th Generation Synchronization‏‎ (19 revisions)
60. VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE‏‎ (18 revisions)
61. Improving Scene Labeling with Hyperspectral Data‏‎ (18 revisions)
62. Flexfloat DL Training Framework‏‎ (18 revisions)
63. David J. Mack‏‎ (18 revisions)
64. Mapping Networks on Reconfigurable Binary Engine Accelerator‏‎ (18 revisions)
65. ASIC Implementation of High-Throughput Next Generation Turbo Decoders‏‎ (18 revisions)
66. Baseband Meets CPU‏‎ (17 revisions)
67. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs‏‎ (17 revisions)
68. Energy Efficient AXI Interface to Serial Link Physical Layer‏‎ (17 revisions)
69. Fast Accelerator Context Switch for PULP‏‎ (17 revisions)
70. Streaming Integer Extensions for Snitch (M)‏‎ (17 revisions - redirect page)
71. Energy Efficient Circuits and IoT Systems Group‏‎ (17 revisions)
72. Compressed Sensing vs JPEG‏‎ (17 revisions)
73. A Snitch-based Compute Accelerator for HERO‏‎ (17 revisions)
74. BLISS - Battery-Less Identification System for Security‏‎ (17 revisions)
75. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (17 revisions)
76. Heterogeneous SoCs‏‎ (16 revisions)
77. Optimal System Duty Cycling for a Mobile Health Platform‏‎ (16 revisions)
78. LightProbe‏‎ (16 revisions)
79. Wireless In Action Data Streaming in Ski Jumping (1 B/S)‏‎ (16 revisions)
80. Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications‏‎ (16 revisions)
81. 3D Turbo Decoder ASIC Realization‏‎ (16 revisions)
82. Rethinking our Convolutional Network Accelerator Architecture‏‎ (16 revisions)
83. Completed‏‎ (15 revisions)
84. Active-Set QP Solver on FPGA‏‎ (15 revisions)
85. Digital Transmitter for Mobile Communications‏‎ (15 revisions)
86. PULP-Shield for Autonomous UAV‏‎ (15 revisions)
87. Vector Processor for In-Memory Computing‏‎ (15 revisions)
88. Elliptic Curve Accelerator for zkSNARKs‏‎ (15 revisions)
89. Big Data Analytics Benchmarks for Ara‏‎ (15 revisions)
90. Digital Beamforming for Ultrasound Imaging‏‎ (15 revisions)
91. Advanced 5G Repetition Combining‏‎ (15 revisions)
92. DMA Streaming Co-processor‏‎ (15 revisions)
93. Design of an LTE Module for the Internet of Things‏‎ (15 revisions)
94. Application Specific Frequency Synthesizers (Analog/Digital PLLs)‏‎ (14 revisions)
95. Ultra low power wearable ultrasound probe‏‎ (14 revisions)
96. ASIC Design of a Gaussian Message Passing Processor‏‎ (14 revisions)
97. Beamspace processing for 5G mmWave massive MIMO on GPU‏‎ (14 revisions)
98. HW/SW Safety and Security‏‎ (14 revisions)
99. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)‏‎ (14 revisions)
100. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (14 revisions)

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