Recent changes
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Track the most recent changes to the wiki on this page.
4 December 2023
| N 14:15 | Modeling FlooNoC in GVSoC (S/M) (diff | hist) . . (+4,093) . . Fischeti (talk | contribs) (Created page with "<!-- Network-on-Chip for coherent and non-coherent traffic (M) --> Category:Digital Category:Network-on-Chip Category:Interconnect Category:GVSoC Category:S...") |
24 November 2023
| 17:47 | Taping a Safer Silicon Implementation of Snitch (M/2-3S) (diff | hist) . . (-1) . . Tbenz (talk | contribs) |
| 17:28 | Main Page (3 changes | history) . . (-97) . . [Gislamoglu (3×)] | |
| 17:28 (cur | prev) . . (0) . . Gislamoglu (talk | contribs) (→Digital Circuits and Systems Group (Prof. Benini)) | ||
| 14:55 (cur | prev) . . (-108) . . Gislamoglu (talk | contribs) (→Digital Circuits and Systems Group (Prof. Benini)) | ||
| 14:53 (cur | prev) . . (+11) . . Gislamoglu (talk | contribs) (→Digital Circuits and Systems Group (Prof. Benini)) |
| 17:28 | Digital (diff | hist) . . (0) . . Gislamoglu (talk | contribs) (→Topic List) |
| 16:05 | Acceleration and Transprecision (diff | hist) . . (-271) . . Fischeti (talk | contribs) |
| 16:04 | Hardware Acceleration (5 changes | history) . . (+18) . . [Fischeti (5×)] | |
| 16:04 (cur | prev) . . (+56) . . Fischeti (talk | contribs) | ||
| 16:03 (cur | prev) . . (+22) . . Fischeti (talk | contribs) (→Matteo Perotti) | ||
| 16:03 (cur | prev) . . (-84) . . Fischeti (talk | contribs) (→Computational Units) | ||
| 16:02 (cur | prev) . . (0) . . Fischeti (talk | contribs) (→Computational Units) | ||
| 16:02 (cur | prev) . . (+24) . . Fischeti (talk | contribs) |
| 14:44 | Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (diff | hist) . . (+5) . . Michaero (talk | contribs) (→References) |
| 01:58 | Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools (diff | hist) . . (+42) . . Kimkwa (talk | contribs) (→Status: Available) |
23 November 2023
| 22:14 | Digital (6 changes | history) . . (+592) . . [Gislamoglu (6×)] | |
| 22:14 (cur | prev) . . (+37) . . Gislamoglu (talk | contribs) (→Topic List) | ||
| 22:14 (cur | prev) . . (0) . . Gislamoglu (talk | contribs) (→Topic List) | ||
| 22:11 (cur | prev) . . (+668) . . Gislamoglu (talk | contribs) | ||
| 22:08 (cur | prev) . . (-36) . . Gislamoglu (talk | contribs) (→Topic List) | ||
| 22:07 (cur | prev) . . (-9) . . Gislamoglu (talk | contribs) (→Topic List) | ||
| 22:05 (cur | prev) . . (-68) . . Gislamoglu (talk | contribs) (→Topic List) |
| 21:55 | GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (diff | hist) . . (-35) . . Gislamoglu (talk | contribs) |
| 21:54 | Cycle-Accurate Event-Based Simulation of Snitch Core (diff | hist) . . (-35) . . Gislamoglu (talk | contribs) |
| N 15:18 | Advanced Data Movers for Modern Neural Networks (4 changes | history) . . (+2,983) . . [Scheremo (4×)] | |
| 15:18 (cur | prev) . . (+46) . . Scheremo (talk | contribs) | ||
| 14:12 (cur | prev) . . (+1) . . Scheremo (talk | contribs) | ||
| 14:11 (cur | prev) . . (+19) . . Scheremo (talk | contribs) | ||
| N | 14:10 (cur | prev) . . (+2,917) . . Scheremo (talk | contribs) (Created page with "==Introduction== In the current era of AI everything, efficient neural network inference has become essential for virtually all edge computing systems, including our very own...") |
| 09:49 | User:Janniss (diff | hist) . . (-1) . . Wiesep (talk | contribs) (→Projects) |
| 09:48 | Investigation of Quantization Strategies for Retentive Networks (1S) (2 changes | history) . . (+4) . . [Wiesep (2×)] | |
| 09:48 (cur | prev) . . (+2) . . Wiesep (talk | contribs) (→Status: Available) | ||
| 09:48 (cur | prev) . . (+2) . . Wiesep (talk | contribs) |
17 November 2023
| 10:30 | Neural Recording Interface and Signal Processing (diff | hist) . . (+48) . . Yiychen (talk | contribs) |
16 November 2023
| 11:25 | Practical Reconfigurable Intelligent Surfaces (RIS) (2 changes | history) . . (+4) . . [Vmenescal (2×)] | |
| 11:25 (cur | prev) . . (+4) . . Vmenescal (talk | contribs) (→Status: Completed) | ||
| 11:23 (cur | prev) . . (0) . . Vmenescal (talk | contribs) (→Status: Available) |
13 November 2023
| 18:31 | Hardware Exploration of Shared-Exponent MiniFloats (M) (diff | hist) . . (+341) . . Lbertaccini (talk | contribs) |
| 18:24 | Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (diff | hist) . . (+26) . . Lbertaccini (talk | contribs) |
| 18:23 | Fault-Tolerant Floating-Point Units (M) (3 changes | history) . . (+728) . . [Lbertaccini; Michaero (2×)] | |
| 18:23 (cur | prev) . . (+537) . . Lbertaccini (talk | contribs) | ||
| 13:50 (cur | prev) . . (+68) . . Michaero (talk | contribs) | ||
| 11:13 (cur | prev) . . (+123) . . Michaero (talk | contribs) |
| N 16:19 | Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) (diff | hist) . . (+1,284) . . Michaero (talk | contribs) (Created page with "<!-- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) --> Category:Digital Category:Fault Tolerance Category:HW/SW Safety and Security Category:2023 [...") |
| 13:44 | A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (diff | hist) . . (+90) . . Michaero (talk | contribs) |
| N 10:56 | Bioprojects (diff | hist) . . (+60) . . Villanif (talk | contribs) (Redirected page to Biomedical Circuits, Systems, and Applications) |
12 November 2023
| 17:23 | Implementation of an Accelerator for Retentive Networks (1-2S) (diff | hist) . . (+62) . . Wiesep (talk | contribs) (→Introduction) |
| 17:23 | Investigation of Quantization Strategies for Retentive Networks (1S) (2 changes | history) . . (+62) . . [Wiesep (2×)] | |
| 17:23 (cur | prev) . . (0) . . Wiesep (talk | contribs) (→Introduction) | ||
| 17:22 (cur | prev) . . (+62) . . Wiesep (talk | contribs) (→Introduction) |
| 17:19 | (Upload log) . . Wiesep (talk | contribs) uploaded File:RetNet.png (Retentive Networks) |
9 November 2023
| N 10:16 | Design of Streaming Data Platform for High-Speed ADC Data (diff | hist) . . (+2,801) . . Yiychen (talk | contribs) (Created page with "== Description == Are you interested in working on cutting-edge technology that involves handling large volumes of high-speed data? We have an exciting opportunity for a motiv...") |
8 November 2023
| 17:30 | Federico Villani (diff | hist) . . (0) . . Villanif (talk | contribs) |
| 17:27 | (Upload log) . . [Yiychen; Villanif] | |
| 17:27 . . Villanif (talk | contribs) uploaded a new version of File:Villanif avatar small.jpg | ||
| 17:20 . . Yiychen (talk | contribs) uploaded File:Spikes.png |
| 17:26 | Neural Recording Interface and Signal Processing (2 changes | history) . . (+20) . . [Yiychen (2×)] | |
| 17:26 (cur | prev) . . (+23) . . Yiychen (talk | contribs) | ||
| 17:22 (cur | prev) . . (-3) . . Yiychen (talk | contribs) (→Description) |
