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Show new changes starting from 22:22, 19 August 2022
   

19 August 2022

     10:09  PULP‎‎ (3 changes | history) . . (+833). . [Kgf‎ (3×)]
      10:09 (cur | prev) . . (+4). . Kgf (talk | contribs) (65nm)
      10:09 (cur | prev) . . (+593). . Kgf (talk | contribs)
      10:01 (cur | prev) . . (+236). . Kgf (talk | contribs) (Related Chips)

18 August 2022

     13:45  MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.‎ (diff | hist) . . (+197). . Meggiman (talk | contribs)
     13:37  Digital‎‎ (3 changes | history) . . (+1,850). . [Meggiman‎ (3×)]
      13:37 (cur | prev) . . (+292). . Meggiman (talk | contribs) (Available Projects)
      13:33 (cur | prev) . . (+1,434). . Meggiman (talk | contribs)
      11:29 (cur | prev) . . (+124). . Meggiman (talk | contribs) (Completed Projects)
     11:24  Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs‎‎ (2 changes | history) . . (+4). . [Meggiman‎ (2×)]
      11:24 (cur | prev) . . (0). . Meggiman (talk | contribs)
      11:23 (cur | prev) . . (+4). . Meggiman (talk | contribs)
     11:22  Designing a Power Management Unit for PULP SoCs‎ (diff | hist) . . (-4). . Meggiman (talk | contribs)
     09:42  Digital Medical Ultrasound Imaging‎ (diff | hist) . . (+204). . Cosandre (talk | contribs)

17 August 2022

 m   09:49  A Unified Compute Kernel Library for Snitch (1-2S)‎‎ (2 changes | history) . . (-2). . [Fischeti‎ (2×)]
 m    09:49 (cur | prev) . . (-2). . Fischeti (talk | contribs)
 m    09:47 (cur | prev) . . (0). . Fischeti (talk | contribs)
     09:46  User:Fischeti‎‎ (2 changes | history) . . (+500). . [Fischeti‎ (2×)]
      09:46 (cur | prev) . . (+249). . Fischeti (talk | contribs)
 m    09:45 (cur | prev) . . (+251). . Fischeti (talk | contribs) (Available Projects)
 m   09:44  Flexfloat DL Training Framework‎‎ (2 changes | history) . . (+4). . [Fischeti‎ (2×)]
 m    09:44 (cur | prev) . . (+2). . Fischeti (talk | contribs)
 m    09:43 (cur | prev) . . (+2). . Fischeti (talk | contribs) (Status: Available)
N    09:35  Design of a Prototype Chip with Interleaved Memory and Network-on-Chip‎ (diff | hist) . . (+2,152). . Fischeti (talk | contribs) (Created page with "<!-- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (1S) --> Category:Digital Category:High Performance SoCs [[Category:Computer Architecture]...")

16 August 2022

N    14:25  User:Colluca‎ (diff | hist) . . (+1,284). . Colluca (talk | contribs) (Created page with "=Luca Colagrande= thumb | 200px| I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineer...")
     14:02  (Upload log). . [Colluca‎ (2×)]
      14:02 . . Colluca (talk | contribs) uploaded File:Colluca picture.png
      13:53 . . Colluca (talk | contribs) uploaded File:Stencils.png(Some example stencil filters)
     13:59  Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)‎‎ (2 changes | history) . . (+95). . [Colluca‎ (2×)]
      13:59 (cur | prev) . . (+24). . Colluca (talk | contribs)
      13:57 (cur | prev) . . (+71). . Colluca (talk | contribs)
     09:32  Digital‎ (diff | hist) . . (+124). . Kgf (talk | contribs) (Completed Projects)
     09:24 (User creation log) . . User account Colluca (talk | contribs) was created by Kgf (talk | contribs) and password was sent by email ‎(Why not :))

15 August 2022

N    19:58  A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)‎ (diff | hist) . . (+2,827). . Nwistoff (talk | contribs) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:FPGA Category:2022 Category:Semester Thesis Category:Bachelor...")
N    18:20  Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)‎ (diff | hist) . . (+2,710). . Tbenz (talk | contribs) (Created page with "<!-- Creating Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Arch...")
N    17:44  MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.‎‎ (6 changes | history) . . (+7,973). . [Pschiavo‎ (6×)]
      17:44 (cur | prev) . . (+1,047). . Pschiavo (talk | contribs) (Status: Available)
      17:42 (cur | prev) . . (+395). . Pschiavo (talk | contribs) (Required Skills)
      17:39 (cur | prev) . . (+12). . Pschiavo (talk | contribs) (Project objectives)
      17:39 (cur | prev) . . (+1,402). . Pschiavo (talk | contribs) (Project description)
      17:34 (cur | prev) . . (+2,903). . Pschiavo (talk | contribs) (Introduction)
N     17:26 (cur | prev) . . (+2,214). . Pschiavo (talk | contribs) (Created page with "==Introduction== Microcontrollers (MCUs) are used in a wide range of applications ranging from sensor-monitoring all the way to robotics. Despite typically lower in performa...")
     17:22  User:Pschiavo‎‎ (2 changes | history) . . (+181). . [Pschiavo‎ (2×)]
      17:22 (cur | prev) . . (+261). . Pschiavo (talk | contribs) (Available projects)
      17:19 (cur | prev) . . (-80). . Pschiavo (talk | contribs) (Pasquale Davide Schiavone)
     17:08  Energy Efficient SoCs‎ (diff | hist) . . (+158). . Pschiavo (talk | contribs)
N    15:31  Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)‎ (diff | hist) . . (+3,280). . Paulsc (talk | contribs) (Created page with "<!-- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2...")
N    14:34  An Efficient Compiler Backend for Snitch (1S/B)‎‎ (2 changes | history) . . (+2,667). . [Paulsc‎ (2×)]
      14:34 (cur | prev) . . (0). . Paulsc (talk | contribs) (Character)
N     14:05 (cur | prev) . . (+2,667). . Paulsc (talk | contribs) (Created page with "<!-- An Efficient Compiler Backend for Snitch (1S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2022 Catego...")
 m   14:06  High Performance SoCs‎‎ (2 changes | history) . . (0). . [Paulsc‎ (2×)]
 m    14:06 (cur | prev) . . (-1). . Paulsc (talk | contribs) (Projects)
 m    14:06 (cur | prev) . . (+1). . Paulsc (talk | contribs) (Available Projects)

12 August 2022

     13:27  Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)‎ (diff | hist) . . (+250). . Mperotti (talk | contribs)
     13:25  RVfplib‎ (diff | hist) . . (-22). . Mperotti (talk | contribs)
 m   11:03  High Performance SoCs‎ (diff | hist) . . (+251). . Fischeti (talk | contribs) (Who are we)

11 August 2022

N    17:04  Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)‎ (diff | hist) . . (+3,887). . Mperotti (talk | contribs) (Created page with "== 1 Project Description and Timeline == Transformers have set a new standard in natural language processing and other recurrent machine learning tasks (e.g., computer vision...")

10 August 2022

     10:22  Marco Bertuletti‎‎ (2 changes | history) . . (+31). . [Mbertuletti‎ (2×)]
      10:22 (cur | prev) . . (+32). . Mbertuletti (talk | contribs)
      10:21 (cur | prev) . . (-1). . Mbertuletti (talk | contribs)
N    10:20  Implementing Configurable Dual-Core Redundancy‎ (diff | hist) . . (+3,774). . Michaero (talk | contribs) (Created page with "<!-- Implementing Configurable Dual-Core Redundancy (1M/S) --> Category:Digital Category:Fault Tolerance Category:HW/SW Safety and Security Category:Computer Ar...")

9 August 2022

     19:19  Marco Bertuletti‎‎ (2 changes | history) . . (-1). . [Mbertuletti‎ (2×)]
      19:19 (cur | prev) . . (-2). . Mbertuletti (talk | contribs)
      19:19 (cur | prev) . . (+1). . Mbertuletti (talk | contribs)