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• Main Page
  ==Selected Projects in Progress== ''For a complete list, see [[:Category:In progress|Projects in Progress]].''
  5 KB (537 words) - 15:22, 23 February 2024
• Ultra-low power processor design
  In this project, you will contribute to a new and exciting project at the IIS ...ded systems. The goal is to achieve a computing platform which is superior in energy efficiency.
  10 KB (1,669 words) - 19:01, 30 January 2014
• Project Meetings
  ...ssistants schedule. These meetings will be used to evaluate the status and progress of the project. Beside these regular meetings, additional meetings can be o
  425 bytes (69 words) - 14:47, 16 January 2014
• Variability Tolerant Ultra Low Power Cluster
  shared-memory cluster realized in 28nm SOI technology. In this project, you By doing this project, you will gain experience in designing strategies for
  3 KB (409 words) - 10:52, 27 March 2014
• Template
  ===Status: In Progress === [[Category:In progress]]
  4 KB (397 words) - 15:44, 14 February 2023
• Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  ...cial challenge pose the high-speed output pin drivers. In case of interest in analog design, investigations and a dedicated layout implementation are wel ...turization allows the physician to carry a small ultrasound imaging device in his pocket which can be used anytime with the same naturalness as the iconi
  4 KB (614 words) - 20:10, 17 February 2015
• Norbert Felber
  == Projects in Progress== category = In progress
  897 bytes (96 words) - 13:56, 18 February 2015
• Flexible Electronic Systems and Embedded Epidermal Devices
  ...ned closely to or even attached to the human body (as epidermal devices). In addition, and through the integration of '''digital electronic components,' ...ignal stack, as well as interface challenges at all levels of integration. In addition, advanced and specialized manufacturing techniques are required fo
  4 KB (444 words) - 12:43, 23 July 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...ial by reorienting the crystal structure and aligning the electric dipoles in the direction of the electric field. ...electric field. The '''frequency response''' of the applied signal results in a '''hysteresis-shaped curve that is used to evaluate the piezoelectric pro
  6 KB (741 words) - 18:14, 21 July 2023
• Weekly Reports
  ...rojects. It is therefore important to update the rest of the group of your progress regularly. One way for such updates are posting weekly reports.if you are w ...in the email, and makes it difficult to link responses to specific points in your email.
  7 KB (1,133 words) - 07:08, 7 October 2023
• Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  ...rove the performance of this parallel bank of ADCs both in the digital and in the analog domain. : Interest in mobile communications
  3 KB (405 words) - 16:13, 29 December 2016
• Digital Transmitter for Mobile Communications
  ...ver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding an
  3 KB (382 words) - 20:00, 26 September 2017
• 3D Turbo Decoder ASIC Realization
  ...plementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology. ===Status: In Progress ===
  3 KB (392 words) - 12:33, 15 April 2016
• Channel Estimation and Equalization for LTE Advanced
  ...mator and equalizer for LTE Advanced. You will compare existing algorithms in MATLAB and come up with an efficient solution suitable for hardware impleme ...rform the back-end design such that the resulting chip can be manufactured in high-end CMOS technology. During this thesis you will get an insight into t
  3 KB (385 words) - 11:13, 14 April 2016
• ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  ...s even further. In this project you will implement a proof-of-concept chip in VHDL, to demonstrate the efficiency of the new architectures. To that end, ...from more theoretical/simulation based projects to the VLSI implementation in form of chip design projects.
  3 KB (508 words) - 11:12, 14 April 2016
• Reconfigurability of SHA-3 candidates
  In December 2010, the 5 finalists of the SHA-3 competition were announced. The : Interest in Cryptography
  2 KB (300 words) - 14:11, 13 March 2014
• Power Optimization in Multipliers
  [[File:Power Optimization in Multipliers.jpg|thumb|160px]] ...lemented with standard-cells and that can be automated in order to be used in a synthesis-based flow.
  3 KB (386 words) - 16:23, 30 October 2020
• Low-power chip-to-chip communication network
  In this work, we will assume that we have already an efficient serial interfac ===Status: In Progress ===
  3 KB (492 words) - 12:34, 7 November 2017
• Accelerators for object detection and tracking
  shared-memory cluster realized in 28nm SOI technology. One of the applications for this system is in real-time video applications, expecially
  3 KB (407 words) - 10:57, 5 November 2019
• Hardware Accelerated Derivative Pricing
  other financial institutions invest heavily in grid computing for them in a Monte-Carlo framework for option pricing. A Matlab framework
  3 KB (429 words) - 09:42, 12 October 2017
• Analog Layout Engine
  ...rogramming languages to automatically generate parametrized cells (PCELLS) in Cadence. ===Status: In Progress ===
  2 KB (329 words) - 17:44, 21 December 2017
• Successive Approximation Register (SAR) ADC
  ===Status: In Progress === [[Category:In progress]]
  2 KB (319 words) - 17:43, 21 December 2017
• Assessment of novel photovoltaic architectures by circuit simulation
  ...fy some of the simulation results experimentally. An extension of the work in form of a master thesis or lab assistant is possible. : Interest in circuit simulation
  3 KB (355 words) - 12:07, 17 January 2014
• Processing of 3D Micro-tomography data for Lithium Ion Batteries
  ...mulations on the already obtained data. The student should have experience in computer programming (preferentially image processing or distributed comput ===Status: In Progress ===
  3 KB (472 words) - 12:12, 17 January 2014
• Developing High Efficiency Batteries for Electric Cars
  ...project is a collaboration with MIT and a battery start-up company located in Cambridge, MA. You will carry out your work at the Integrated Systems Labor : Interest in 3D Modelling
  3 KB (389 words) - 12:28, 17 January 2014
• Simulation of Li-ion batteries and comparison with experimental data
  ...e capacity of batteries is becoming a critical issue in our modern society in order to fully exploit the potential of renewable energies such as wind or : Interest in Device Modelling
  3 KB (362 words) - 15:43, 4 September 2019
• Ab-initio Simulation of Strained Thermoelectric Materials
  ...e3, PbTe, or PbSe. If ZT>2 values are obtained, the work will be published in a journal paper. ===Status: In Progress ===
  3 KB (456 words) - 15:43, 4 September 2019
• Implementation of a 2-D model for Li-ion batteries
  Standard 1-D simulation models, as popularized in the mid 90's, are computationally very efficient to fulfill this task, but ===Status: In Progress ===
  3 KB (431 words) - 15:41, 4 September 2019
• Putting Together What Fits Together - GrÆStl
  ...and hash algorithms are two of the most important cryptographic primitives in security protocols. ...alists of the NIST SHA-3 hash competition, which presented its winner late in 2012.
  3 KB (434 words) - 12:01, 26 March 2015
• High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  In order to fulfill today’s high-throughput requirements in secure environments with data rates beyond 100 Gbit/s, so-called authentica ...e of operation (GCM-AES) represents a de-facto standard in the literature. In this project we investigate potential high-speed alternatives to GCM- AES b
  3 KB (392 words) - 12:25, 26 March 2015
• A Multiview Synthesis Core in 65 nm CMOS
  ...9) renders content creation an increasingly difficult process, and results in higher transmission bandwith and storage requirements. Moreover, the number The ASIC developed in this project implements an image domain warping (IDW) based rendering stage
  4 KB (524 words) - 15:49, 13 May 2015
• Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  ...ll image patches around those interest points are extracted and normalized in size. Third, feature descriptors are calculated from those normalized patch ...nses are thresholded in order to yield a binary descriptor, which is small in size and can be matched very efficiently using the Hamming distance.
  3 KB (487 words) - 15:57, 13 May 2015
• Compressed Sensing Reconstruction on FPGA
  ...rithms were found to benefit strongly from parallel processing. Challenges in the design were parallel memory access to provide input for all multipliers ...RTL implementations of the two similar algorithms allowed for comparisons in terms of resource usage and performance. We could show which algorithm perf
  3 KB (389 words) - 18:56, 28 January 2014
• Pirmin Vogel
  ...from the Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland, in 2013 and 2018, respectively. During his Ph.D. his research focus was on dig ...ombination of skills, expertise and vision. Since Nov 2019, Pirmin is back in the Integrated Systems Laboratory where he is working for lowRISC.
  1 KB (193 words) - 15:39, 3 March 2020
• Image Sensor Interface and Pre-processing
  ...o access data from the image sensors. The main part of the project will be in designing the pre-processing stage which will perform a set of filtering an : Interest in video processing and machine learning
  3 KB (357 words) - 18:53, 6 December 2014
• Digitally-Controlled Analog Subtractive Sound Synthesis
  ...th popular synthesizers from Moog Music, Sequential, ARP Instruments, etc. In recent years, building such music synthesizers became accessible and afford ...oftware must be developed in order to control the synthesizer's parameters in real-time.
  5 KB (597 words) - 12:56, 4 December 2021
• IcySoC
  ...of the integrated circuit design using reliable transistors, particularly in Complementary Metal-Oxide-Semiconductor (CMOS) technology. However, semicon ...rch and data mining, lend themselves readily for such a design philosophy. In fact, all of which can tolerate inaccuracies to varying extents or can synt
  4 KB (568 words) - 12:48, 9 February 2015
• A Wireless Sensor Network for a Smart LED Lighting control
  ...ghting control can be made based on the light intensity and human presence in the monitored area sensed by light sensors and motion sensors. This approac ...e students. Measurements of the system will be performed from the students in order to evaluate power consumption reduction, reliability, functionality a
  3 KB (487 words) - 12:02, 27 January 2016
• Accelerator for Spatio-Temporal Video Filtering
  large optimization problems in real-time is difficult and sometimes even unfeasible. However, the mathemat ...r filtering in the spatial and temporal domain. These filters scale better in terms of computational complexity than the corresponding optimization probl
  3 KB (366 words) - 12:40, 1 June 2017
• Sandro Belfanti
  ...ical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis
  2 KB (336 words) - 17:27, 1 November 2017
• Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
  [[Category:In progress]]
  2 KB (225 words) - 14:58, 8 March 2014
• Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
  ...dingten Sachzwängen (Timing, Latenz, Protokoll, Interface, Taktung, usw.) in einer elektronischen Schaltung steht diesem Bedürfnis im Wege. Ausgehend v [[Category:In progress]]
  2 KB (217 words) - 15:00, 8 March 2014
• Glitches Reduce Listening Time of Your iPod
  [[File:Power Optimization in Multipliers.jpg|thumb]] ...and to investigate various glitch reduction techniques for their efficency in reducing glitching power and suitability for incorporation into an automati
  2 KB (330 words) - 15:59, 14 September 2017
• Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  : Interest in high-performance mixed signal circuit design; : Background in hardware design and low-level sofware implementation (e.g. VHDL or assemble
  2 KB (307 words) - 20:06, 17 February 2015
• Audio DAC Conversion Jitter Measurement System
  : Interest in high-performance mixed signal circuit design : Experience in analog circuit design beneficial
  2 KB (251 words) - 20:06, 17 February 2015
• Improving Scene Labeling with Hyperspectral Data
  ...very interesting opportunities to outperform even the best-trained humans; in fact you can see it as a step towards spectroscopic analysis of materials. ...YPERSPECTRAL%20SNAPSHOT%20MOSAIC%20IMAGER%2020150421.pdf pdf]] and adopted in first industrial computer vision cameras [[http://www.ximea.com/files/broch
  6 KB (941 words) - 11:29, 5 February 2016
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  Current interest in brain-inspired and neuromorphic computer architectures is enormous, due to ...u will integrate the complete accelerator inside the PULP platform (either in the simulation platform or the FPGA emulation platform).
  5 KB (784 words) - 14:50, 30 November 2016
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  These days, security breaches are omnipresent in our daily news thanks to the NSA and others. Therefore, new cryptographic a ...ikipedia.org/wiki/Advanced_Encryption_Standard AES]. If you are interested in working on hardware implementations of state-of-the-art security algorithms
  2 KB (317 words) - 13:13, 14 April 2016
• Android Software Design
  ...th improved display, signal processing for, e.g., heart-beat rate read-out in an ECG is desirable. The software should further include a GUI for the conf ===Status: In Progress ===
  2 KB (278 words) - 16:57, 12 July 2022
• Investigation of the source starvation effect in III-V MOSFET
  ...ion model capable of capturing the distribution of the electron population in the source contact of III-V MOSFETs and of determining whether or not sourc : Interest in device modeling
  3 KB (331 words) - 15:40, 4 September 2019
• Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  ...mulator what happens if the GaAsSb/InP junction contains atomic roughness. In this case, momentum conservation is broken and L-valley electrons might eve : Interest in device modeling
  3 KB (377 words) - 15:44, 4 September 2019
• Design study of tunneling transistors based on a core/shell nanowire structures
  ...could provide better performance than standard ones. The key idea consists in using a core/shell nanowire structure where the core and the shell have dif : Interest in device modeling
  3 KB (357 words) - 15:38, 4 September 2019
• Computation of Phonon Bandstructure in III-V Nanostructures
  [[File:Computation of Phonon Bandstructure in III-V Nanostructures.png|280px|thumb]] ...ld's summation method in bulk structures, it is not clear how to handle it in nanostructures without too much increasing the computational burden.
  3 KB (363 words) - 15:37, 4 September 2019
• Simulation of Negative Capacitance Ferroelectric Transistor
  ...ring ON-OFF switching processes. In FETs, the major difficulty to overcome in order to minimize their power consumption is the value of their inverse sub ===Status: In Progress ===
  3 KB (449 words) - 15:37, 4 September 2019
• Investigation of Redox Processes in CBRAM
  ...a large number of different metal/oxide pairs so that their applicability in CBRAM applications can be validated. ...developed an electrochemical model in COMSOL to simulate ON/OFF switching in CBRAM. So far, the model still depends on a number of free input parameters
  4 KB (488 words) - 17:12, 16 September 2021
• Investigation of Metal Diffusion in Oxides for CBRAM Applications
  ...umber of metal/oxide pairs and analyze them regarding their applicability in CBRAM applications ...group has developed a model in COMSOL to simulate ON/OFF switching in CBRAM. So far, the model depends on a number of free input parameters, amon
  3 KB (448 words) - 17:11, 16 September 2021
• Development of an efficient algorithm for quantum transport codes
  :Good knowledge in solid state physics and quantum mechanics ===Status: In Progress ===
  2 KB (284 words) - 17:10, 16 September 2021
• Integrated silicon photonic structures
  physical effect available in integrated photonics circuits has been a scientific and internship project is placed in the heart of our R&D activities and covers topics related
  4 KB (608 words) - 13:58, 23 June 2021
• Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  ...ch means the high purity frequency carriers are required to be synthesized in the range from 15 GHz to even 60 GHz. ...lution (PLL), VCO is the key part of the whole frequency solution since it in general consumes 70% to even 80% of the full power budget of a PLL as well
  4 KB (518 words) - 16:07, 6 May 2019
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  In addition to the "pseudo-processor-controlled approach", the [[Category:In progress]]
  2 KB (326 words) - 12:26, 26 March 2015
• Hardware Support for IDE in Multicore Environment
  [[File:Hardware support for IDE in multicore.jpg|thumb]] ===Status: In Progress ===
  2 KB (188 words) - 10:58, 27 March 2014
• FPGA-Based Digital Frontend for 3G Receivers
  ...n receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received ...s in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE).
  2 KB (348 words) - 20:01, 26 September 2017
• ASIC
  In an ASIC (Application Specific Integrated Circuit) project you will be worki ...nding on the project, your design may be sent for manufacturing to be used in future projects.
  1 KB (165 words) - 19:52, 10 February 2015
• FPGA
  ...prototypes and/or testbeds used to simulate the behavior of large systems. In such a project you will ==Projects in Progress==
  1,020 bytes (132 words) - 19:50, 10 February 2015
• Indoor Positioning with Bluetooth
  : Interest in wireless communications : Knowledge in Matlab, C and/or VHDL is of advantage
  3 KB (449 words) - 12:12, 4 November 2019
• Advanced 5G Repetition Combining
  ...s to a brute-force approach to combining this information. As a first step in your project, you will study ways to reduce the complexity on an algorithmi ===Status: In Progress ===
  3 KB (345 words) - 10:52, 5 April 2022
• OpenRISC SoC for Sensor Applications
  ...cessor design | previous semester thesis]]. We are already using this core in our [[:Category:PULP|multi-core projects]] and we continue to make improvem : SPI is used as a standard interface in many applications, especially in resource limited systems where the number of I/O pins are limited. We alrea
  4 KB (667 words) - 15:23, 23 December 2016
• Hardware Accelerator for Model Predictive Controller
  In the latest years model predictive controller has been successfully applied ...ion enabling the use of model predictive control in a real case scenario. In addition to that thermal evolution of multicore platforms are characterized
  3 KB (456 words) - 08:35, 20 January 2021
• NORX - an AEAD algorithm for the CAESAR competition
  A detailed description of the algorithm can be found in the specification [http://competitions.cr.yp.to/round1/norxv1.pdf PDF]. ===Status: In Progress ===
  3 KB (423 words) - 11:13, 13 June 2014
• Digital Beamforming for Ultrasound Imaging
  ...n body, with both diagnostic and therapeutic applications. IIS is involved in a project developing a high-performance, portable 3D ultrasound platform. ...r elements, it is definitely the computationally most intensive operation. In order to allow for portable 3D ultrasound systems, new algorithms and hardw
  3 KB (423 words) - 11:23, 10 November 2017
• An FPGA-Based Evaluation Platform for Mobile Communications
  In this project you will implement a simulation environment for mobile communi All parts of a wireless receiver have to be carefully optimized in order to
  3 KB (413 words) - 16:05, 21 July 2016
• Real-Time Pedestrian Detection For Privacy Enhancement
  ...n public places are being monitored: real-time surveillance is not allowed in such cases, and stored data can (even for internal use) only be accessed wi : Interest in video processing and machine learning
  3 KB (408 words) - 13:17, 5 February 2016
• Karim Badawi
  == Projects in Progress== category = In progress
  653 bytes (63 words) - 15:06, 5 December 2018
• GSM Voice Capacity Evolution - VAMOS
  ...Evolved EDGE even allows 1 Mobile Station (MS) to use 2 frequency carriers in the downlink. This further provides less time slots available for Voice con ...ections are transmitted simultaneously on the same time slot. This results in 4 simultaneous voice connections if half rate voice codecs are used. The VA
  2 KB (250 words) - 17:45, 14 April 2016
• Design of an LTE Module for the Internet of Things
  ...g low-power and low-cost of IoT components, especially on the client side. In the latest release of the LTE standard, a new user-equipment category (Cat- ...owards Category-0 devices. In a second stage you will implement the design in a hardware description language (HDL) and deploy it to the LTE transceiver
  3 KB (335 words) - 14:20, 4 November 2019
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...n public places are being monitored: real-time surveillance is not allowed in such cases, and stored data can (even for internal use) only be accessed wi
  9 KB (1,289 words) - 19:45, 24 March 2015
• Low-power Clock Generation Solutions for 65nm Technology
  planning a series of [[PULP]] chips in this technology. Depending on the 100 and 800 MHz. In this work, a low power clock generation solution is
  3 KB (466 words) - 19:37, 3 March 2016
• Evaluating the RiscV Architecture
  ...de size etc.) The plan is to manufacture the Risc V based [[PULP]] cluster in UMC 65nm technology, to obtain also measurement results. ===Status: In Progress ===
  3 KB (374 words) - 16:24, 30 October 2020
• Hardware/software co-programming on the Parallella platform
  [[Category:In progress]]
  3 KB (501 words) - 14:26, 2 September 2015
• Gomeza old project4
  ...ency and generality than traditional computer vision techniques. With that in mind, we want to explore their effectiveness on batteryless (e.g. solar-pow ===Status: In Progress ===
  3 KB (480 words) - 19:08, 28 January 2017
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  ...portant as a high-efficiency is controllability: lowest energy consumption in VLSI chips requires several dynamically adaptable voltages: # Unused units need to be fully shut down due to the leakage present even in absence of clock and signal transitions.
  3 KB (438 words) - 18:06, 3 February 2015
• Gomeza old project1
  ...geneity has been a common approach to reach this goal in high-end systems. In this project, your main task will be to design and implement an energy-awar ...rallelism, a typical application can be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, a
  3 KB (431 words) - 18:04, 28 January 2017
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  ...ess sensors are most commonly used for monitoring, detection of events and in general collecting/processing/sending sensors data (i.e temperature, humidi ...sing of the data could be part of the project as well. The project is done in collaboration with Institute of Neuroinformatics Prof. Richard Hahnloser
  4 KB (589 words) - 10:14, 3 August 2018
• Gomeza old project2
  ...ying capacity. By the end of this project a functional node will be tested in a simulated environment. ===Status: In Progress ===
  3 KB (376 words) - 18:04, 28 January 2017
• Energy Neutral Multi Sensors Wearable Device
  ...mount of easily obtained prior information without resorting to supervised in situ training. ===Status: In Progress ===
  2 KB (319 words) - 16:24, 30 October 2020
• Digital
  ...f the time negotiable with the supervisor. Don't hesitate to show interest in a master thesis topic even though you are e.g. looking for a semester thesi ...our projects categories or added a new project, you need to open this page in edit mode and save it (without changing anything) for the list to get refre
  7 KB (811 words) - 15:21, 23 February 2024
• Acceleration and Transprecision
  ...cient. Such accelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cr ===Projects In Progress===
  2 KB (275 words) - 17:05, 24 November 2023
• Telecommunications
  ...telecommunications. Feel free to contact them if you want to do a project in this field. ==Projects in Progress==
  892 bytes (86 words) - 17:42, 24 March 2015
• Ultrafast Medical Ultrasound imaging on a GPU
  In conventional ultrasound imaging each image line is acquired sequentially. S In ultrafast imaging, on the other hand, the entire field of view is acquired
  3 KB (428 words) - 12:13, 1 August 2018
• Philipp Schönle
  ==Projects in Progress== category = In progress
  569 bytes (54 words) - 10:52, 10 March 2015
• Benjamin Sporrer
  ==Projects in Progress== category = In progress
  567 bytes (54 words) - 13:01, 10 March 2015
• Real-Time Optical Flow Using Neural Networks
  ...others work by looking at few well-trackable points (corners, edges, ...) in both images to find correspondences and then solve complex optimization pro ...re computer vision is most interesting: on low-power and mobile platforms, in cars, ...
  5 KB (707 words) - 11:22, 5 February 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...re virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires the programmer to manual ...TCDM to filter the accelerator's accesses to shared data structures living in main memory, and to spare the programmer from manually setting up the DMA t
  5 KB (716 words) - 13:43, 29 November 2019
• DigitalUltrasoundHead
  ...r a large cable containing hundreds of small coaxial cables. This is shown in the figure below: We plan to replace this analog connection by a digital link as shown in the next figure:
  3 KB (378 words) - 11:52, 10 January 2017
• Audio
  ==Projects in Progress== category = In progress
  403 bytes (36 words) - 17:28, 11 February 2015
• Pascal Hager
  == Projects in Progress== category = In progress
  775 bytes (81 words) - 11:40, 10 November 2017
• Software
  In this category the projects require you to do programming ==Projects in Progress==
  473 bytes (46 words) - 13:45, 8 August 2016
• Vector Processor for In-Memory Computing
  ...ors - and these would have direct access to the DRAM. The concept of such "in-memory computing" ...so far it has not been viable on an industrial scale. Recent developments in process technology combined with industrial efforts to bring them
  3 KB (443 words) - 13:10, 2 November 2015
• Signal to Noise Ratio Estimation for 3G standards
  ...to-noise ratio (SNR) is the basis for almost any digital signal processing in a receiver. ...semester project you will implement an efficient SNR-estimation algorithm in order to obtain an energy and area-efficient solution. This can be done as
  2 KB (300 words) - 11:23, 14 April 2016
• FFT-based Convolutional Network Accelerator
  ...or FPGA accelerator to perform this step faster and more power-efficiently in the frequency domain. * Interest in computer vision, signal processing and VLSI design
  8 KB (1,145 words) - 11:30, 5 February 2016
• High-speed Scene Labeling on FPGA
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...are codesign work is much more applicable in industry and less constrained in terms of memory and interfaces. If desired by the student, also the use of
  8 KB (1,197 words) - 18:18, 29 August 2016
• Michael Muehlberghuber
  ...an the ones listed below. So just drop me an e-mail or come into my office in order to discuss any security- or cryptography-related topics. ===Projects in Progress===
  1 KB (139 words) - 12:39, 7 November 2017
• Cryptography
  ...eld of cryptography. Feel free to contact them if you want to do a project in this field. <!-- ==Projects in Progress==
  645 bytes (67 words) - 21:04, 24 August 2018
• Time Synchronization for 3G Mobile Communications
  ...are around and which synchronization codes are used. Solving this problem in dedicated hardware will be the topic of this thesis. Synchronization in time will detect the position of the frame boundaries and reveal the Cell I
  3 KB (420 words) - 11:22, 14 April 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...on to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. Based on a content-addressable memory (CAM), e ...L. Benini, "Lightweight Virtual Memory Support for Many-Core Accelerators in Heterogeneous Embedded SoCs", ''Proceedings of the 10th International Confe
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...on to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. Based on a content-addressable memory (CAM), e ...with a multi-level TLB and lightweight hardware support for TLB management in order to support dynamic self-updating of the TLB without frequent host int
  4 KB (554 words) - 17:57, 7 November 2017
• Autonomous Sensing For Trains In The IoT Era
  ...and railways applications in collaboration with Bombardier that (i) can go in a zero-power but with change status fast when important events are detected
  6 KB (774 words) - 08:36, 23 November 2022
• Switched Capacitor Based Bandgap-Reference
  ...or driven by a posititive to absolute temperature (PTAT) current to result in a temperature independent voltage of about 1.2V. Such a voltage is not comp ...they create an intrinsic voltage ripple that has to be heavily suppressed in the case of a reference.
  4 KB (471 words) - 11:13, 3 May 2018
• Scattering Networks for Scene Labeling
  ...es) were successfully employed in a number of classification tasks [1,3]. In contrast to traditional convolutional neural networks which learn the filt ===Status: {Available, Reserved, In Progress, Completed}===
  4 KB (563 words) - 11:29, 5 February 2016
• Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  ...uccess in wearable devices and sensors in several real-world applications. In this project we address the challenges of context recognition on low energy You will investigate the possibility to implement neural network in a ultra low power energy efficient micro-controller (Ambiq Apollo). The mai
  4 KB (507 words) - 12:11, 16 February 2016
• Low Power Neural Network For Multi Sensors Wearable Devices
  ...itoring, and detection of events related to the wearer (e.g. abnormalities in physiological functions, detection of seizures and symptoms, patterns of mo ...rate (e.g. sampling frequency) sufficient for the particular application, in order not to miss the event. However, the rate of occurrence of the event
  7 KB (895 words) - 17:02, 28 July 2017
• GUI-developement for an action-cam-based eye tracking device
  ...ior of novice and expert athletes and the ability to drive in the elderly. In such cases, it is impertinent to record the participants’ behavior under ...t, pause, stop) and all its settings. The live preview should be displayed in the app and a possibility to incorporate a live eye position overlay should
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• David J. Mack
  ...ard Karls University in Tübingen, Germany. In 2015, he acquired his Ph.D. in Cognitive and Behavioral Neuroscience at the same university. Since 2015 he If you are interested in eye tracking, biological signal processing or even a neuroscience research
  2 KB (310 words) - 17:41, 31 August 2016
• Improving our Smart Camera System
  ...sify every pixel in an image using convolutional neural networks. However, in the mean time we have developed several new approaches to process the acqui Now we would like to include those in our prototype, and otherwise improve it by building a more compact system,
  8 KB (1,176 words) - 16:26, 30 October 2020
• Implementing Hibernation on the ARM Cortex M0
  ...rocontroller in this environment requires special measurements to be taken in order to avoid restarting the entire task after each power outage. Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibernation''
  3 KB (390 words) - 11:59, 20 June 2016
• Ultra-Efficient Visual Classification on Movidius Myriad2
  ...lown floating point data that is often unnecessary to achieve good results in trained models. On the other hand, ASICs are often orders of magnitude more ...yriad architecture can provide more than 10 GOPS of processing performance in a power envelope of less than 0.5W. It consists of two general-purpose SPAR
  4 KB (593 words) - 14:57, 30 November 2016
• Efficient Implementation of an Active-Set QP Solver for FPGAs
  Quadratic programming (QP) problems arise in various embedded optimization applications such as model predictive control In this master project you will be working on an efficient FPGA implementation
  4 KB (542 words) - 12:39, 1 June 2017
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...stem on a FPGA and further improve the accelerator. This is where you come in. We have several aspects which we would like to explore: porting the Origam
  3 KB (397 words) - 18:17, 29 August 2016
• Learning Image Decompression with Convolutional Networks
  In this project, we have developed several ConvNets to remove compression arti ===Status: {Available, Reserved, In Progress, Completed}===
  2 KB (285 words) - 18:16, 29 August 2016
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
  ...ULP) accelerators we are developing the first Computer Vision (CV) library in such domain. ...form designed to operate on a large range of operating voltages, achieving in this way a high level of energy efficiency over a wide range of application
  4 KB (628 words) - 16:16, 20 February 2018
• Gomeza old project3
  ...harvesting applications, sensor nodes are able to store any excess energy in a storage device such as battery or supercapacitor for future use. A correc # Test final design in real-world scenarios
  3 KB (366 words) - 18:04, 28 January 2017
• Bateryless Heart Rate Monitoring
  ...ombination wearable sensors and wireless communication. We are interested in building small wearable, bateryless devices which can perform different dif # Test final design in real-world scenarios.
  3 KB (413 words) - 15:21, 28 January 2016
• Change-based Evaluation of Convolutional Neural Networks
  ...e next (consider a fixed camera and just some people or cars moving around in the scene). This project would look into updating intermediate results only * Interest in computer vision and system engineering
  5 KB (747 words) - 18:04, 29 August 2016
• Rethinking our Convolutional Network Accelerator Architecture
  ...ns such as the synthesis-time fixed filter sizes and room for improvements in terms of energy efficiency. We are looking for your creativity to completel * Interest in VLSI architecture exploration and computer vision
  9 KB (1,263 words) - 18:52, 12 December 2016
• Using Motion Sensors to Support Indoor Localization
  sound, optical, vision, or a combination of them. In the context of low-cost embedded systems, as observed in some previous work [1]. This project abstracts from the specific localizati
  3 KB (426 words) - 11:41, 21 July 2017
• Turbo Equalization for Cellular IoT
  ...ds which is one of the reasons why Turbo equalization is found only seldom in practical receiver implementations today. ...ution can be completely hidden making Turbo equalization a viable solution in practical communication systems.
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...on to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs [1,2]. Recently, we have switched to a new eval ...to be adapted to use the widely adopted AXI4 protocol [6], which has built-in cache control signals that shall be used by your new IP. Besides designing
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  [[File:channel_decoder_intro.jpg|thumb|400px|Channel Decoder in Today's Communication Systems]] ...TE standard bases for example on Turbo codes, LDPC codes have been adopted in the Wifi standard IEEE802.11n/ac/ax. With that the question arises: What co
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  [[File:channel_decoder_intro.jpg|thumb|400px|Channel Decoder in Today's Communication Systems]] ...TE standard bases for example on Turbo codes, LDPC codes have been adopted in the WiFi standard IEEE802.11n/ac/ax. With that the question arises: What co
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• Implementation of a NB-IoT Positioning System
  ...een satellite and receiver making the location estimation very inaccurate. In indoor environments satellite-based positioning completely fails. Furthermo ...DOA) algorithm the base stations transmit reference signals as illustrated in the figure. The User Equipment (UE) detects the time difference of arrival
  4 KB (555 words) - 16:36, 23 May 2018
• Towards Self Sustainable UAVs
  '''Motivation''' In recent years, the popularity of unmanned aerial vehicles (UAV’s) has soar ...on, it suffers from very large charging times and very short flight times. In this
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• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...easily portable to other host CPU architectures, but it cannot be executed in interrupt context which causes substantial scheduling delays and an overall ...orted to a dedicated microcontroller core inside the RAB or be implemented in dedicated hardware. While the first step allows to remove the scheduling de
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...nt of the page size of the Linux operating system running on the host CPU. In a student project [4], a second, set-associative IOTLB has been designed wh ...d with the accelerator is placed in this section, requiring a single entry in the first IOTLB only.
  6 KB (866 words) - 13:43, 29 November 2019
• Self-Learning Drones based on Neural Networks
  Neural Nets are achieving record-breaking results in all common machine learning tasks and reached high attention of the machine ...nd made the headline by beating the 2nd best player in the world Lee Sedol in the game Go [1]. A game which were considered to be too complex to be solve
  6 KB (828 words) - 16:26, 20 February 2018
• Ultra Low Power Conversion Circuit For Batteryless Applications
  ...the expensive and obtrusive storage element. One of the biggest challenges in batteryless system design is the cold start phase, where the harvesting cir ...10 uW input power range, they are unable to operate in the nanowatt range. In this project, we want to design a DC-DC converter optimized for very low in
  3 KB (485 words) - 17:46, 10 August 2016
• Gomeza old project5
  ...ave several prototypes of batteryless sensor nodes which we want to deploy in a wide area network. * Integrating a LoRa radio in a batteryless sensor node
  3 KB (360 words) - 18:25, 28 January 2017
• 3D Ultrasound Bubble Tracking
  ...Ultrafast Ultrasound Localization Microscopy (uULM) [http://fultrasound.eu/in-vivo-super-resolution-vascular-imaging link]. This semester/master thesis focuses on the ultrafast tracking of bubbles in 3D.
  2 KB (253 words) - 20:52, 12 November 2020
• Towards The Integration of E-skin into Prosthetic Devices
  ...n) and energy harvesting during the project. The project will be supervise in collaboration with Cosmic Lab, University of Genova (prof. Maurizio Valle / ...lations), measuring power-consumption, and assessing detection performance in lab. conditions
  4 KB (631 words) - 11:39, 21 July 2017
• A Wireless Sensor Network for a Smart Building Monitor and Control
  ...ghting control can be made based on the light intensity and human presence in the monitored area sensed by light sensors and motion sensors. This approac ...e students. Measurements of the system will be performed from the students in order to evaluate power consumption reduction, reliability, functionality a
  4 KB (571 words) - 21:42, 30 July 2018
• A Wireless Sensor Network for HPC monitoring
  The rapid progress of wireless communications and embedded technologies has made wireless sens ...e students. Measurements of the system will be performed from the students in order to evaluate power consumption reduction, reliability, functionality a
  5 KB (617 words) - 16:22, 27 February 2018
• Mauro Salomon
  == Projects in Progress== category = In progress
  637 bytes (60 words) - 10:47, 5 April 2022
• Charging System for Implantable Electronics
  such an extent that its size is small enough to be implantable in rodents for charge the implant's battery while the animal is in its cage from an IR-LED
  3 KB (366 words) - 13:05, 27 April 2018
• Libria
  == Projects in Progress== category = In progress
  646 bytes (68 words) - 09:35, 26 August 2016
• Learning Image Compression with Convolutional Networks
  ...a ConvNet for a different encoding has been done several times before, but in order to optimize for best compression we need to quantize intermediate res In this project you learn the basics of ConvNets, develop such a quantization
  3 KB (362 words) - 16:25, 30 October 2020
• Bringing XNOR-nets (ConvNets) to Silicon
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...it/pixel instead of ~12bit/pixel like before. The current state-of-the-art in this direction are XNOR-nets, but we want to understand them better and use
  10 KB (1,357 words) - 16:25, 30 October 2020
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...t run-time. Aiming at bridging this gap, we designed and developed at IIS, in collaboration with some Commercial Partners, a scalable and highly accurate [[Category:In progress]]
  3 KB (351 words) - 16:19, 27 February 2018
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...t run-time. Aiming at bridging this gap, we designed and developed at IIS, in collaboration with some Commercial Partners, a scalable and highly accurate ...t''' → Implementation and testing of a Linux Device Driver for the built-in Beaglebone Black ADC, using DMA support for the data-copy from the ADC HW-F
  3 KB (394 words) - 16:19, 27 February 2018
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...t run-time. Aiming at bridging this gap, we designed and developed at IIS, in collaboration with some Commercial Partners, a scalable and highly accurate ...te a high-speed high-resolution ADC, which will be controlled by the built-in Programmable Real-Time Unit ([http://beagleboard.org/pru PRU]) of the Beagl
  3 KB (440 words) - 16:15, 1 September 2017
• Open Power-On Chip Controller Study and Integration
  In recent years, energy-efficiency is becoming a key challenge in the High Performance Computing (HPC) domain. Until today Intel-based comput ...aracterizing its behavioral (B) and implementing an extension of the built-in power management policy (C) which links run-time architectural information,
  3 KB (462 words) - 15:57, 9 September 2016
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
  In recent years, energy-efficiency is becoming a key challenge in the High Performance Computing (HPC) domain. Indeed, while the demand for m ...experience with Linux Kernel Programming, IIO Linux Subsystem (widely used in Linux-Based SoCs for handling ADCs) and architectural performance counters.
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• Ultra Low-Power Oscillator
  ...research results and to achieve a comparable efficiency as the best design in the figure. ===Status: In Progress ===
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• High performance continous-time Delta-Sigma ADC for biomedical applications
  ...us-time converter for up to 10kHz bandwidth with 80dB SNR will be designed in 130nm CMOS. It will be possible to learn the whole the design cycle includi ===Status: In Progress ===
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• High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  ...ll be investigated first at behavioral level, followed by a circuit design in 130nm CMOS. It will be possible to learn the whole the design cycle includi ===Status: In Progress ===
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• PVT Dynamic Adaptation in PULPv3
  ...controller algorithm is then needed to always configure the PULP processor in the most energy efficient point. The goal of this project is to compensate the process variation in the PULP v3 SoCs by (1) characterize and correlate the PVT sensors respons
  3 KB (348 words) - 15:31, 13 September 2016
• Design of low-offset dynamic comparators
  ...ated comparators with similar delay time (determined by the clock period). In this thesis different topologies will be compared to each other for resolut ===Status: In Progress ===
  3 KB (362 words) - 17:35, 21 December 2017
• Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
  consists in applying electronic warfare concepts to estimate the conducted in collaboration with said company. Information on the
  4 KB (609 words) - 11:38, 21 July 2017
• Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  ...o life several months without change the battery. THe project will be done in collaboration with Keyfinder.ch : Interest in Computer Architectures at system level
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• High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  ...t imposed by cellular applications have been a key driver for PLL research in recent years. As the age of cellular internet of things is coming, motivati ===Status: In Progress ===
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• High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  ...project is to analyze and build a time domain ADC innovatively so that the in-band jitter contribution of the DPLL could be lower than 500fs while consum ===Status: In Progress ===
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• Design of Charge-Pump PLL in 22nm for 5G communication applications
  ...ch means the high purity frequency carriers are required to be synthesized in the range from 15 GHz to even 60 GHz. ...n in the figure above, there are quite many smart architectures introduced in recent years, such as injection-locking (ILPLL) and subsampling (SSPLL). Al
  4 KB (514 words) - 15:51, 20 August 2021
• Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  ...quantum-transport based hybrid plasmonic laser simulator by extending our in-house quantum-transport solver with electron-photon coupling. The functiona ...by using plasmonics. By coupling photons to collective motion of electrons in metals, surface plasmon polaritons (SPPs) are formed at a metal/dielectric
  2 KB (323 words) - 17:09, 16 September 2021
• Sensor Fusion for Rockfall Sensor Node
  ...complete reconstruction of the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information can be eval
  2 KB (352 words) - 11:51, 21 August 2018
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...the past two years. PULP is intended to be used for near-sensor computing in smart sensors, particularly on sensors that have a high need for extremely ...icial cochlea strives to replicate this functionality in a silicon sensor. In nature, the spiking representation conveys enough information for us to rec
  9 KB (1,427 words) - 18:36, 5 September 2019
• Towards Online Training of CNNs: Hebbian-Based Deep Learning
  ...s possible to greatly reduce the amount of data that needs to be collected in a ULP sensor node and sent to a higher-level computing device (e.g. a smart 2. implement Adaptive Hebbian Learning (AHL) as proposed in Wadhwa and Madhow [Wadhwa16] within the framework, using classification of
  6 KB (909 words) - 19:50, 30 May 2017
• Deep Learning Projects
  ...gradient descent) is linear in the data set size, making it more appealing in big data contexts than, for instance, support vector machines (SVMs). DNNs ...the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two families of optimizations:
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• Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  ...s possible to greatly reduce the amount of data that needs to be collected in a ULP sensor node and sent to a higher-level computing device (e.g. a smart ...icial cochlea strives to replicate this functionality in a silicon sensor. In nature, the spiking representation conveys enough information for us to rec
  6 KB (920 words) - 16:33, 3 October 2019
• Single-Bit-Synapse Spiking Neural System-on-Chip
  Current interest in brain-inspired and neuromorphic computer architectures is enormous, due to ...starting point for the development of a novel spiking-based architecture, in this project we would like to develop a concrete proof of concept low power
  7 KB (1,000 words) - 12:22, 13 January 2017
• Tiny CNNs for Ultra-Efficient Object Detection on PULP
  ...s possible to greatly reduce the amount of data that needs to be collected in a ULP sensor node and sent to a higher-level computing device (e.g. a smart ...e-of-the-art. Relatively small CNNs with object detection accuracy results in the order of the best models available have recently been proposed [Iandola
  5 KB (794 words) - 13:19, 13 January 2017
• PULP-Shield for Autonomous UAV
  ...s the inspection of industrial facilities or cultivated fields, assistance in natural disaster or hazardous areas, etc. ...no-scale, featuring only few centimeters in diameter and few tens of grams in weight.
  6 KB (875 words) - 11:06, 23 February 2018
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  Neural Nets are achieving record-breaking results in all common machine learning tasks and reached high attention of the machine ...own to be reduced by about 10% or less. (75% instead of 85% Top-1 accuracy in the sound recognition CNN.)
  6 KB (823 words) - 08:36, 20 January 2021
• VLSI Implementation Polar Decoder using High Level Synthesis
  ...nnels. This is why Polar codes have been one of the main focus of research in the communication’s society. The recent decision by the 3GPP standardizat ...architectures can be quantitatively evaluated based on the generated RTL. In order to improve the quality of results, manually optimized RTL code or eve
  3 KB (392 words) - 14:17, 5 April 2022
• FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  ...all these use cases makes new communication protocols inevitable resulting in today’s IoT standardization efforts including cellular IoT (Extended-Cove ...the work throughout the project requires embedded C coding, with some work in HDL being required eventually.
  3 KB (462 words) - 13:54, 13 November 2020
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  ...most failure mechanisms and noise. There have been successful applications in variety of tasks such as: language recognition, text classification, biosig In this project, your goal would be to develop an RTL implementation of HD com
  4 KB (467 words) - 13:38, 10 November 2020
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  ...which can be exploited by an application-specific integrated circuit ASIC, in contrast to CPUs or even GPUs. In this thesis, the students will develop an optimized Deconvolution Accelerat
  6 KB (842 words) - 08:37, 20 January 2021
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...level semantically rich information out of raw data is deep learning, and in particular deep convolutional neural networks (CNNs). The task of inference ...tand-alone ASICs for aggressively quantized CNNs (''YodaNN'' [Andri2017]), in the Ergo project we want to design a PULP-based entire computation cluster
  6 KB (949 words) - 13:41, 10 November 2020
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  ...past with our platform, with the additional advantage of more flexibility in the target application. ...ith the shared memory of the PULP clusters. Techniques and ideas developed in the context of PULP HW accelerators [Conti2017][Azarkhish2017] can be used
  6 KB (916 words) - 15:50, 7 December 2018
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  ...ip asynchronously outputs a stream of address-events representing activity in different audio frequency ranges. ...difference (ITD); in other words, the difference in the azimuth direction in the arrival timing of sound waves, at the two ears. Similarly to what is do
  7 KB (1,025 words) - 19:52, 30 May 2017
• A computational memory unit using phase-change memory devices
  ...ces are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. ...riety of application areas such as machine learning and signal processing. In IBM Research - Zurich we have shown experimental demonstrations of this con
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  ...akes it particularly challenging, however, is its susceptibility to errors in the recognition of human intentions. Indeed, the recent success of deep lea ===Status: In Progress ===
  3 KB (372 words) - 20:22, 1 April 2019
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
  ...orking principles of the brain, allowed to achieve superhuman performances in many fields, redefining the state of the art for computer vision, text and ...fixed-point precision arithmetic, aligned with the standard precision used in deep learning field.
  7 KB (1,001 words) - 10:43, 26 June 2017
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  ...ting platforms, allowing to implement resilient controllers. Its tolerance in low signal-to-noise ratio (SNR) conditions and for faulty components is ach In this project, your goal would be to design and develop an end-to-end robust
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  ...ing up silicon quickly and makes a software developer's life a lot easier. In smaller processors like the ones developed at IIS we rely on an external de External, in-contrast to self-hosted, debugging relies on a more powerful host machine a
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  ...tor by using a distance metric. When the dimensionality of hypervectors is in the thousands (e.g.,100,000 bits), an efficient search operation is challen ...l would be to design an efficient and general module for search operations in HD computing. You would develop RTL implementation with FPGA prototyping.
  3 KB (366 words) - 15:39, 10 November 2020
• BigPULP: Multicluster Synchronization Extensions
  ...stantial number of tape outs of various single-cluster PULP configurations in multiple technology nodes [1]. A key component allowing for high energy-eff ...formance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integration
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...stantial number of tape outs of various single-cluster PULP configurations in multiple technology nodes [1]. A key component allowing for high energy-eff ...formance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integration
  6 KB (801 words) - 15:05, 23 August 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  ...al component or its immediate neighbors. Other operations can be performed in a distributed fashion. ...omputational paradigm that is easily applied to various learning problems. In this project, your goal is to accelerate, optimize, and autotune execution
  3 KB (409 words) - 13:58, 9 November 2017
• Stefan Lippuner
  Stefan left the IIS in 2022. == Projects in Progress==
  532 bytes (49 words) - 10:47, 24 November 2022
• LTE IoT Network Synchronization
  ...ings. Two new variants of LTE have been standardized as part of Release 13 in 2016 for this kind of device: LTE Cat-M1 (eMTC) and NB-IoT. They both offer Network synchronization is the first step in the communication between the user equipment (UE) and the base station. It
  3 KB (440 words) - 16:32, 18 May 2018
• IoT Turbo Decoder
  ...ceived data iteratively. Several Turbo Decoders have been developed at IIS in the past ([[High_Throughput_Turbo_Decoder_Design|e.g.]]), which were mainly ...the IoT, a new variant of LTE have been standardized as part of Release 13 in 2016: LTE Cat-M1 (eMTC). This category offers only a reduced throughput of
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...pa.phys.ethz.ch/ Physics Department of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real wor ...ssues a signal for data taking or not). The Xilinx AC701 Development Board in combination with a recently designed and build interface board (see picture
  4 KB (460 words) - 21:42, 30 January 2018
• Satellite Internet of Things
  ...d in fact the extended-coverage would enable communication with satellites in Low Earth Orbits (LEO). But, the NB-IoT standard is optimized for slowly mo ...able the identification of critical bottlenecks. These shall be eliminated in the second part of the project by algorithmic optimizations and/or changes
  3 KB (393 words) - 13:53, 13 November 2020
• Neural Networks Framwork for Embedded Plattforms
  ...like Torch or Tensorflow to evaluate and train the network and export it in a compilable form for efficient inference on the previously mentioned platf [[Category:In progress]]
  3 KB (317 words) - 14:40, 14 April 2021
• BLISS - Battery-Less Identification System for Security
  ...the significant power consumption prevent this technology to be exploited in small, wearable, battery-powered and autonomous devices. ...task, the project is split into 2 projects, which can possibly be combined in the end.
  4 KB (602 words) - 10:45, 31 January 2023
• HERO: TLB Invalidation
  ...stantial number of tape outs of various single-cluster PULP configurations in multiple technology nodes. ...formance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integration
  6 KB (796 words) - 17:19, 18 November 2019
• Shared Correlation Accelerator for an RF SoC
  ...rk synchronization rely on performing a large number of cross-correlations in real-time. Due to the large throughput requirements, large accelerators are ...cross-correlations. Using this knowledge, you will develop the accelerator in VHDL, or using High-Level Synthesis (HLS). It should be able to meet the th
  3 KB (421 words) - 09:38, 14 September 2018
• Deep Convolutional Autoencoder for iEEG Signals
  In this thesis, the students will develop a deep convolutional autoencoder to * project report (in digital form; a hard copy also welcome, but not necessary)
  5 KB (641 words) - 13:36, 9 September 2020
• Heterogeneous SoCs
  ...le:Apple_heterogeneous_integration.png|700px|thumb|center|Uniting many ICs in a single one: Heterogeneous integration has allowed (not only) Apple to get ...currently one of the main drivers for performance-per-energy advancements in various application domains.
  3 KB (421 words) - 18:41, 28 October 2020
• Event-Driven Computing
  ...orth to run expensive computations or whether there is not enough activity in the environment. This approach is called event-driven computing. ===Projects In Progress===
  2 KB (266 words) - 11:16, 5 November 2020
• Predictable Execution
  ...on the same chip as the host CPU, sharing a single DRAM. This has benefits in both programability and performance, due to the removal of the need for dat ...l-time guarantees can be provided, enabling the use of these architectures in a real-time setting.
  2 KB (286 words) - 18:48, 10 November 2020
• Aliasing-Free Wavetable Music Synthesizer
  ...digital signal processors (DSPs) or field-programmable gate arrays (FPGAs) in order to generate the wavetable synthesis oscillator signals, to the best o ...LAB with the goal of minimizing aliasing while offering great flexibility. In the second step, a VLSI architecture and ASIC will be designed. The goal is
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  ...IC that provides a large number of freely programmable operators resulting in endless sound-design possibilities compared to existing FM synthesizers. ...imultaneous voices). Third, the student(s) will implement the architecture in a modern CMOS process and send the modular FM synthesis ASIC to fabrication
  5 KB (549 words) - 12:35, 28 November 2022
• Digital Medical Ultrasound Imaging
  ...s include the efficient processing and transmission of this data off-head. In addition, we are actively working on developing strategies to manage the po ...project area. If you are interested in the topic and want to do something in the areas mentioned above, come to see us to discuss up-to-date project opp
  6 KB (797 words) - 16:16, 23 February 2024
• Hyperdimensional Computing
  ...at can enable fast and one-shot learning (no need of back-propagation like in neural networks). Furthermore it is memory-centric with embarrassingly para ...and one-shot learning make HD computing a prime candidate for utilization in application domains such as: brain-computer interfaces, biosignal processin
  10 KB (1,341 words) - 10:46, 25 April 2018
• Level Crossing ADC For a Many Channels Neural Recording Interface
  ...tal Converters (LC-ADC) could reduce the amount of information to transfer in case of low activity of the input signal, compared to more common Uniform-S In this project, it is proposed to the student the implementation of a low-pow
  4 KB (616 words) - 19:10, 29 January 2021
• Integrated Information Processing
  ...thz.ch Integrated Information Processing (IIP) Group] carries out research in the following areas: rect 2853 1 3702 740 [[All-Digital In-Memory Processing]]
  7 KB (814 words) - 16:53, 8 January 2024
• Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
  ...networks and other machine learning approaches accurately predict patterns in image and time-based data when large historical datasets with curated datas ...y living of elderly and to evaluate psychological and physiological stress in firemen by using leading hardware (HW) accelerators.
  7 KB (1,003 words) - 17:30, 6 December 2021
• Andreas Kurth
  ==Projects in Progress== category = In progress
  1 KB (123 words) - 07:40, 11 June 2021
• CMOS power amplifier for field measurements in MRI systems
  ...modalities in medical diagnostics and research. One of the foremost trends in MRI technology has been multiple‐channel signal acquisition with detector ...amplifier is necessary. In this project such an amplifier (NMR Probe Amp. in the picture) will be designed an ev. also implemented. The thesis offers th
  3 KB (354 words) - 16:06, 6 May 2019
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...much more efficiently than current computer technology for certain tasks. In this project, your goal will be to implement real-time quantum state identi ...u will use a Virtex-6 FPGA to perform quantum signal processing operations in real time, and an FMC110 ADC board to sample analog signal outputs of Circu
  5 KB (599 words) - 09:03, 21 December 2017
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
  ...lized on the same chip, it will demonstrate the first 25 Gbps optical link in a zero-change CMOS technology. ===Status: In Progress ===
  3 KB (382 words) - 11:44, 20 August 2021
• Inductive Charging Circuit for Implantable Devices
  Implantable devices have seen a large growth in the past years. For humans pacemakers are most common, but more recently ot ...arging will be investigated. It includes the whole transfer chain as shown in the picture, with the transmit driver, the coils and the charging part on t
  3 KB (329 words) - 11:43, 20 August 2021
• Low Power Geolocalization And Indoor Localization
  ...g products and people’s everyday life. Sensors and wearable technologies in particular are gaining popularity, with people surrounded by everything... ...he moving target can help improving the localization precision as observed in some previous work [1]. This project abstracts from the specific localizati
  5 KB (697 words) - 13:36, 11 January 2018
• Wake Up Radio For Energy Efficient Communication System and IC Design
  ...ition, a low power solution, should include addressing capability directly in the wake-up receiver. ...ts of the system will be performed from the students as important activity in order to evaluate power consumption, reliability, functionality, classifica
  5 KB (686 words) - 11:54, 2 February 2018
• Zero Power Touch Sensor and Reciever For Body Communication
  ...The receiver can be used both as an always-on touch sensor to be deployed in the field and as a body communication wake up radio to other nodes on the h ...ts of the system will be performed from the students as important activity in order to evaluate power consumption, reliability, functionality, classifica
  4 KB (585 words) - 11:58, 2 February 2018
• Sub-Noise Floor Channel Tracking
  ...ings. Two new variants of LTE have been standardized as part of Release 13 in 2016 [2] for this kind of device: LTE Cat-M1 (eMTC) and NB-IoT. They both o ...mation eventually limits the achievable coverage. In LTE reference symbols in each subframe are used to estimate the channel for the same subframe. Impro
  4 KB (481 words) - 16:33, 18 May 2018
• A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  * Familiarity with embedded/parallel programming in C. * project report (in digital form; a hard copy also welcome, but not necessary)
  4 KB (605 words) - 16:35, 20 February 2018
• Monocular Vision-based Object Following on Nano-size Robotic Blimp
  * Familiarity with embedded system programming in C. * project report (in digital form; a hard copy also welcome, but not necessary)
  5 KB (623 words) - 16:14, 20 February 2018
• Towards Autonomous Navigation for Nano-Blimps
  ...led balloon, the energy requirement for hovering is significantly reduced. In this project we aim to extend the functionality of our first self-sustainab ...end the existing self-sustainable blimp developed at TIK/IIS and presented in [3].
  7 KB (1,008 words) - 16:20, 20 February 2018
• Study and Development of Intelligent Capability for Small-Size UAVs
  ...med in order to study the portability and to overcome eventual limitations in the initial MCU. ...on capability where the UAV is able to collected data from sensor deployed in a field.
  6 KB (842 words) - 16:18, 20 February 2018
• Towards Self-Sustainable Unmanned Aerial Vehicles
  ...on, it suffers from very large charging times and very short flight times. In this project, we explore another type of UAV, a blimp, whose helium-filled ...used to directly power the blimp, either in a slow continuous movement, or in a burst-like fashion.
  6 KB (914 words) - 16:17, 20 February 2018
• Stefan Mach
  ==Projects in Progress==
  1 KB (117 words) - 17:06, 29 July 2020
• Fabian Schuiki
  ...ssionate Rust and C++ programmer and occupies himself with compiler design in his free time. ==Projects in Progress==
  1 KB (126 words) - 11:02, 21 February 2018
• Real-Time ECG Contractions Classification
  ...equence of atrial and ventricles contractions allow the blood to be pumped in the circulatory systems, essential to enable many physiological functions a ...CG monitoring is currently limited to short-time scales (minutes to hours) in well controlled environments and setups (clinics, expensive devices).
  4 KB (597 words) - 19:15, 9 March 2020
• Evaluating An Ultra low Power Vision Node
  ...occur and entering an idle mode when there are no events. This can be used in the context of machine learning to only trigger network inference when even In this project, a novel event-driven camera by Qualcomm will be evaluated and
  3 KB (433 words) - 15:16, 4 August 2022
• SW/HW Predictability and Security
  We are in the processes of creating a top-level information page, in the meantime please continue directly to the specific subsections below. Please continue to [[Real-Time Embedded Systems]] if you are interested in designing hardware or writing software for timing predictable embedded syst
  1 KB (155 words) - 21:03, 19 November 2021
• Digital Audio Interface for Smart Intensive Computing Triggering
  ...ve already achieved very promising results in this direction. The drawback in such applications is that, to achieve reasonably good classification accura A very promising approach to avoid wasting power in processing meaningless data (e.g. when just noise is coming from a sensor)
  4 KB (649 words) - 17:27, 22 January 2019
• Predictable Execution on GPU Caches
  ...only offer a major increase in performance, but also promises an increase in energy efficiency due to the use of more efficient accelerators. However, c ...program when the system is not permitting memory accesses from the program in question, the memory phase is tasked with copying all data needed for compu
  5 KB (706 words) - 17:41, 19 June 2019
• Freedom from Interference in Heterogeneous COTS SoCs
  ...only offer a major increase in performance, but also promises an increase in energy efficiency due to the use of more efficient accelerators. However, c ...pplications that can be executed concurrently on a heterogeneous platform, in accordance with the PREM model. The main outcome of the project is to gain
  4 KB (499 words) - 17:40, 19 June 2019
• Pulse Oximetry Fachpraktikum
  ...of generating and acquiring signals used in 'photoplethysmography' (PPG). In this thesis, the goal is to '''create''' a new Fachpraktikum where students Each improvement step is compared in size and power with the previous version.
  3 KB (358 words) - 15:59, 18 February 2019
• Wearables for Sports and Life Enhancement
  ===Status: In Progress === [[Category:In progress]]
  3 KB (381 words) - 14:17, 28 January 2023
• Engineering For Kids
  To promote the engineering profession and studies in (primary+) schools we're developing an interesting edutainment system for k ...tation which will coordinate and connect the different mini-tasks together in order for a whole group or class to achieve a common goal. This thesis invo
  3 KB (447 words) - 16:11, 18 September 2018
• Improved Reacquisition for the 5G Cellular IoT
  ...ower-Graph-1024x659.jpg|600px|thumb|LTE Cat-M1 Power Consumption over time in discontinuous reception [1].]] ...hey only receive at certain pre-defined moments (paging occasions) and are in stand-by most of the time. The range between these moments can range from m
  3 KB (346 words) - 14:04, 11 January 2021
• Improving Cold-Start in Batteryless And Energy Harvesting Systems
  ...distributed fashion has required low-power, battery-based sensing systems. In recent years, batteryless sensing systems have received attention from the In batteryless sensing systems, the smaller the energy storage capacity, the f
  5 KB (638 words) - 15:41, 10 November 2020
• Ultra-low power sampling front-end for acquisition of physiological signals
  ...a switched capacitor circuit before converting it into the digital domain. In this thesis it will be possible to learn the whole the design cycle includi ===Status: In Progress ===
  2 KB (359 words) - 16:06, 6 May 2019
• OTDOA Positioning for LTE Cat-M
  ...een satellite and receiver making the location estimation very inaccurate. In indoor environments satellite-based positioning completely fails. Furthermo In the adopted Observed Time Difference of Arrival (OTDOA) algorithm the base
  4 KB (566 words) - 15:50, 9 February 2021
• Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
  ...ty will first be investigated at a functional level before implementing it in a CMOS process. ===Status: In Progress ===
  2 KB (356 words) - 15:55, 6 May 2019
• Optimal System Duty Cycling for a Mobile Health Platform
  As in every clocked digital circuit, the power consumption consists of leakage po ...urally, this process consumes parasitic energy, labeled E_reboot in the figure.
  4 KB (597 words) - 16:57, 12 July 2022
• Ultra-low power transceiver for implantable devices
  ...a 130nm CMOS technology and offers to design radio and base-band circuits. In the thesis it will be possible to learn the whole the design cycle includin ===Status: In Progress ===
  2 KB (347 words) - 11:43, 20 August 2021
• An Industrial-grade Bluetooth LE Mesh Network Solution
  Routing is a critical issue in packet-switched networks, such as Bluetooth Low Energy (BLE) meshes, due to ...itting data periodically to a network gateway (which is a default use case in many industrial applications).
  5 KB (685 words) - 15:34, 10 November 2020
• Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
  ...environment and collect individual-level exposure data is a crucial aspect in keeping the workforce and our loved ones safe and healthy. Apart from gas c ...to explore efficient ways to extract relevant information (Sensor Fusion) in real-time on resource-constraint, Bluetooth Low Energy IoT devices.
  5 KB (622 words) - 15:36, 10 November 2020
• Embedded Gesture Recognition Using Novel Mini Radar Sensors
  ...of the system will be performed from the students as an important activity in order to evaluate power consumption, reliability, functionality, classifica ...lations), measuring power-consumption, and assessing detection performance in lab. Conditions
  5 KB (631 words) - 15:36, 10 November 2020
• Physics is looking for PULP
  ...tial to discover new and potentially useful phenomena in condensed matter. In such environments, you often have to build new and customized measurement a The group is interested in deploying FPGAs in several of their systems. As a start they would like to have a simple FPGA
  4 KB (497 words) - 16:50, 21 June 2018
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
  ...eurons. Contrarily to what happens in neural recording employing tetrodes, in this scenario, the data streams that reflect the underlying neuron activity ...er that can be dissipated by brain tissues. In order to achieve this goal, in a second phase of the project we aim at designing a dedicated hardware engi
  5 KB (741 words) - 10:05, 18 November 2019
• Human Intranet
  ...such systems prototyped or envisioned today serve to address deficiencies in the human sensory or motor control systems due to birth defects, illnesses, Here, in our projects, we mainly focus on '''sensor, computation, communication, and
  17 KB (2,419 words) - 20:09, 10 March 2024
• Low Latency Brain-Machine Interfaces
  ===Status: In Progress === * project report (in digital form; a hard copy also welcome, but not necessary)
  4 KB (594 words) - 09:18, 16 September 2021
• A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  ...bacteriuria. Approximately one-third of urinary catheters are applied not in the context of enabling the release of urine, but instead, are used to moni In this project, we aim to develop an alternative, non-invasive method to meas
  6 KB (857 words) - 15:37, 10 November 2020
• Indoor Smart Tracking of Hospital instrumentation
  ...cuff as a source if its use is linked to the infected patients. Moreover, in case of a single incidence of infection, equipment that has come into con ...best technology in terms of lifetime and precision,and he will evaluate it in University Hospital Zurich.
  6 KB (780 words) - 15:37, 10 November 2020
• Ultrasound High Speed Microbubble Tracking
  ...Ultrafast Ultrasound Localization Microscopy (uULM) [http://fultrasound.eu/in-vivo-super-resolution-vascular-imaging link]. In a first project, we successfully managed to demonstrate detection and track
  3 KB (391 words) - 20:49, 12 November 2020
• Wireless Sensing With Long Range Comminication (LoRa)
  ...enging to be achieved in practice since low power microprocessors are weak in terms of computation power. High computation microprocessor are power hungr .... RISC-V has the advantage that it is open-source and avoids license fees. In this thesis, typical image processing or neural network algorithms needs to
  5 KB (744 words) - 15:37, 10 November 2020
• Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
  ...ess sensors are most commonly used for monitoring, detection of events and in general collecting/processing/sending sensors data (i.e temperature, humidi ...sing of the data could be part of the project as well. The project is done in collaboration with Institute of Neuroinformatics Prof. Richard Hahnloser
  4 KB (594 words) - 15:38, 10 November 2020

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