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• Modeling FlooNoC in GVSoC (S/M)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  4 KB (520 words) - 15:15, 4 December 2023
• Energy Efficient AXI Interface to Serial Link Physical Layer
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  2 KB (250 words) - 18:21, 20 February 2023
• High Performance SoCs
  ===[[:User:Fischeti| Tim Fischer]]=== * '''e-mail''': [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  11 KB (1,337 words) - 10:54, 25 January 2024
• Flexfloat DL Training Framework
  * Contact: [[:User:Paulin | Gianna Paulin]], [[:User:Fischeti | Tim Fischer]] [[Category:Fischeti]]
  4 KB (613 words) - 10:13, 2 November 2022
• A Unified Compute Kernel Library for Snitch (1-2S)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  4 KB (554 words) - 09:49, 17 August 2022
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]] : [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  8 KB (1,304 words) - 14:44, 23 October 2023
• Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  2 KB (308 words) - 14:30, 8 March 2023
• AXI-based Network on Chip (NoC) system
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  2 KB (252 words) - 14:43, 23 October 2023
• Network-on-Chip for coherent and non-coherent traffic (M)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  3 KB (332 words) - 14:29, 24 October 2023
• Network-off-Chip (M)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  4 KB (586 words) - 14:27, 24 October 2023
• Routing 1000s of wires in Network-on-Chips (1-2S/M)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  3 KB (511 words) - 16:23, 31 October 2023
• Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
  ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  4 KB (530 words) - 10:50, 3 November 2023
• Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  2 KB (332 words) - 11:18, 3 November 2023
• Efficient collective communications in FlooNoC (1M)
  [[Category:Fischeti]] ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
  6 KB (897 words) - 19:52, 22 February 2024